AMS73CAG01808RA Datasheet, PDF (8/31 Pages) Advanced Monolithic Systems Ltd – HIGH PERFORMANCE 1Gbit DDR3 SDRAM

AMS73CAG01808RA
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff.
The Mode Register 1 is written by asserting low on CS, RAS, CAS, WE, high on BA0, low on BA1 and BA2,
while controlling the states of address pins according to the table below.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 _{Address Field}
0*¹
01
0*¹ Qoff TDQS 0*¹ Rtt_Nom 0^*1 Level Rtt_Nom D.I.C
AL Rtt_Nom D.I.C DLL Mode Register 1
A11 TDQS enable
0
Disabled
1
Enabled
A7 Write leveling enable
0
Disabled
1
Enabled
A4 A3
00
01
10
11
Additive Latency
0 (AL disabled)
CL-1
CL-2
Reserved
A12
Qoff ^*2
0
Output buffer enabled
1
Output buffer disabled ^*2
*2: Outputs disabled - DQs, DQSs, DQSs.
BA1 BA0
0
0
0
1
1
0
1
1
MRS mode
MR0
MR1
MR2
MR3
A9 A6 A2
Rtt_Nom ^*3
000
001
010
011
100
101
110
111
ODT disabled
RZQ/4
RZQ/2
RZQ/6
RZQ/12*⁴
RZQ/8*⁴
Reserved
Reserved
Note : RZQ = 240 ohms
A0 DLL Enable
0
Enable
1 Disable
*3: In Write leveling Mode (MR1[bit7] = 1)
with MR1[bit12] = 1, all RTT_Nom settings
are allowed; in Write Leveling Mode
(MR1[bit7] = 1) with MR1[bit12] = 0, only
RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
*4: If RTT_Nom is used during Writes,
only the values RZQ/2,RZQ/4 and RZQ/6
are allowed.
A5 A1
00
01
10
11
Output Driver Impedance Control
RZQ/6
RZQ/7
RZQ/TBD
RZQ/TBD
Note : RZQ = 240 ohms
* 1 : BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
AMS73CAG01808RA Rev. 1.0 December 2010
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