A43E06321 Datasheet, PDF (6/46 Pages) AMIC Technology – 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM

A43E06321
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD and VSS
CDC1
0.1 + 0.01
µF
Decoupling Capacitance between VDDQ and VSSQ
CDC2
0.1 + 0.01
µF
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0ºC to +70ºC for commercial or TA = -40ºC to +85ºC for extended)
Symbol
Parameter
Operating Current
Icc1 _{(One Bank Active)}
Test Conditions
Burst Length = 1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA
Speed
-75
-95
40
Units Note
mA 1
Icc2 P
Icc2 PS
Precharge Standby Current
in power-down mode
CKE ≤ VIL(max), tCC = 15ns
CKE ≤ VIL(max), tCC = ∞
0.3
mA
0.5
ICC2N
ICC2NS
Precharge Standby Current
in non power-down mode
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.
5.5
2
mA
ICC3P Active Standby current in
CKE ≤ VIL(max), tCC = 15ns
1.5
non power-down mode
mA
(One Bank Active)
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
ICC3N
Input signals are changed one time during 30ns
12
Operating Current
ICC4 _{(Burst Mode)}
IOL = 0mA, Page Burst
All bank Activated, tCCD = tCCD (min)
45
mA 1
ICC5 Refresh Current
ICC6 Self Refresh Current
tRC ≥ tRC (min)
CKE ≤ 0.2V
2 Banks
1 Banks
60
mA 2
100
uA
80
ICC7 Deep Power Down Current CKE ≤ 0.2V
10
uA
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
PRELIMINARY (July, 2005, Version 0.0)
5
AMIC Technology, Corp.