A43E06321 Datasheet, PDF (39/46 Pages) AMIC Technology – 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM

Mode Register Set Cycle
0
CLOCK
1
2
3
4
5
6
CKE
CS
*Note 2
High
RAS
CAS
ADDR
WE
* Note 1
* Note 3
Key
Ra
DQM
DQ
Hi-Z
Auto Refresh Cycle
A43E06321
0
1
2
3
4
5
6
7
8
9
10
High
tRC
Hi-Z
MRS
New
Command
Auto Refresh
New Command
: Don't care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1. CS, RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
PRELIMINARY (July, 2005, Version 0.0)
38
AMIC Technology, Corp.