A25LQ32A Datasheet, PDF (6/59 Pages) AMIC Technology – 32Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory

SPI OPERATIONS
Standard SPI Instructions
The A25LQ32A is accessed through an SPI compatible bus
consisting of four signals: Serial Clock (C), Chip Select ( S ),
Serial Data Input (DI), and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write
instructions, addresses or data to the device on the rising
edge of Serial Clock (C). The DO output pin is used to read
data or status from the device on the falling edge of Serial
Clock (C).
Dual SPI Instructions
The A25LQ32A supports Dual SPI operation when using the
“FAST_READ_DUAL_OUTPUT and FAST_READ_DUAL_
INPUT_OUTPUT” (3B and BB hex) instructions. These
instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices.
The Dual Read instructions are ideal for quickly downloading
code to RAM upon power-up (code-shadowing) or for
executing non-speed-critical code directly from the SPI bus
(XIP). When using Dual SPI instructions the DI and DO pins
become bidirectional I/O pins; IO0 and IO1.
Quad SPI Instructions
The A25LQ32A supports Quad SPI operation when using the
“FAST_READ_QUAD_OUTPUT” (6B hex) and
“FAST_READ_QUAD_INPUT_OUTPUT”
(EB
hex)
instructions. This instruction allows data to be transferred to
or from the device four to six times the rate of ordinary Serial
Flash. These 2 instructions offer a significant improvement in
continuous and random access transfer rates allowing fast
code-shadowing to RAM or execution directly from the SPI
bus (XIP). When using Quad SPI instructions the DI and DO
pins become bi-directional IO0 and IO1, and the W and
HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
A25LQ32A Series
Hold Condition
The Hold ( ^HOLD ) signal is used to pause any serial
communications with the device without resetting the clocking
sequence. However, taking this signal Low does not
terminate any Write Status Register, Program or Erase cycle
that is currently in progress. The ^HOLD function is only
available for standard SPI and Dual SPI operation, not during
Quad SPI.
To enter the Hold condition, the device must be selected, with
Chip Select ( ^S ) Low.
The Hold condition starts on the falling edge of the Hold
(^HOLD ) signal, provided that this coincides with Serial Clock
(C) being Low (as shown in Figure 2.).
The Hold condition ends on the rising edge of the Hold
(^HOLD ) signal, provided that this coincides with Serial Clock
(C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after
Serial Clock (C) next goes Low. This is shown in Figure 2.
During the Hold condition, the Serial Data Output (DO) is high
impedance, and Serial Data Input (DI) and Serial Clock (C)
are Don’t Care.
Normally, the device is kept selected, with Chip Select ( ^S )
driven Low, for the whole duration of the Hold condition. This
is to ensure that the state of the internal logic remains
unchanged from the moment of entering the Hold condition.
If Chip Select ( ^S ) goes High while the device is in the Hold
condition, this has the effect of resetting the internal logic of
the device. To restart communication with the device, it is
necessary to drive Hold ( ^HOLD ) High, and then to drive Chip
Select ( ^S ) Low. This prevents the device from going back to
the Hold condition.
Figure 2. Hold Condition Activation
C
HOLD
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
(March, 2012, Version 1.4)
5
AMIC Technology Corp.