A25LQ32A Datasheet, PDF (28/59 Pages) AMIC Technology – 32Mbit, 3V Suspend/Resume, Dual/Quad-I/O Serial Flash Memory

Page Program (PP)
The Page Program (PP) instruction allows bytes to be
programmed in the memory (changing bits from 1 to 0).
Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip
Select ( ^S ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data Input
(DI). If the 8 least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end of the
current page are programmed from the start address of the
same page (from the address whose 8 least significant bits
(A7-A0) are all zero). Chip Select ( ^S ) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in Figure 16. If more than
256 bytes are sent to the device, previously latched data are
discarded and the last 256 data bytes are guaranteed to be
A25LQ32A Series
programmed correctly within the same page. If less than 256
Data bytes are sent to device, they are correctly programmed
at the requested addresses without having any effects on the
other bytes of the same page.
Chip Select ( ^S ) must be driven High after the eighth bit of the
last data byte has been latched in, otherwise the Page
Program (PP) instruction is not executed.
As soon as Chip Select ( ^S ) is driven High, the self-timed
Page Program cycle (whose duration is t_PP) is initiated. While
the Page Program cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed
Page Program cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
BP0) bits (see table 1) is not executed.
Figure 16. Page Program (PP) Instruction Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (02h)
24-Bit Address
Data Byte 1
DI
23 22 21 3 2 1 0 ₇ 6 5 4 3 2 1 0
MSB
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
Data Byte 2
Data Byte 3
Data Byte 256
DI
76543210 76543210 76543210
MSB
MSB
MSB
Note: Address bits A23 to A22 are Don’t Care, for A25LQ32A.
(March, 2012, Version 1.4)
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AMIC Technology Corp.