A43E16161_15 Datasheet, PDF (42/48 Pages) AMIC Technology – 1M X 16 Bit X 2 Banks Low Power Synchronous DRAM

A43E16161
Function Truth Table (Table 1)
Current
State
CS RAS CAS _WE BA
Address
Action
HX XXX
X
NOP
L H HHX
X
NOP
LHHLX
X
ILLEGAL
IDLE
L
H
L
X BA CA, A10/AP ILLEGAL
L
L
H H BA
RA
Row Active; Latch Row Address
L
L
H
L BA
PA
NOP
L
L
L
HX
X
Auto Refresh or Self Refresh
L
L
L
L
OP Code
Mode Register Access
HX XXX
X
NOP
L H HHX
X
NOP
Row
LHHLX
X
ILLEGAL
Active
L
H
L
H BA CA,A10/AP Begin Read; Latch CA; Determine AP
L
H
L
L BA CA,A10/AP Begin Write; Latch CA; Determine AP
L
L
H H BA
RA
ILLEGAL
L
L
H
L BA
PA
Precharge
L
L
L
XX
X
ILLEGAL
HX XXX
X
NOP(Continue Burst to End →Row Active)
L H HHX
X
NOP(Continue Burst to End →Row Active)
LHHLX
X
Term burst →Row Active
Read
L
H
L
H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
LH
L L BA
CA,AP Term burst; Begin Write; Latch CA; Determine AP
L
L
H H BA
RA
ILLEGAL
L
L
H
L BA
PA
Term Burst; Precharge timing for Reads
L
L
L
XX
X
ILLEGAL
HX XXX
X
NOP(Continue Burst to End→Row Active)
L H HHX
X
NOP(Continue Burst to End→Row Active)
LHHLX
X
ILLEGAL
Write
L
H
L
H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
L
H
L
L BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
L
L
H H BA
RA
ILLEGAL
L
L
H
L BA
A10/AP Term Burst; Precharge timing for Writes
L
L
L
XX
X
ILLEGAL
HX XXX
X
NOP(Continue Burst to End→Precharge)
L H HHX
Read with
Auto
LHHLX
X
NOP(Continue Burst to End→Precharge)
X
ILLEGAL
Precharge _L
H
L
H BA CA,A10/AP ILLEGAL
L
H
L
L BA CA,A10/AP ILLEGAL
L
L
H X BA
RA, PA ILLEGAL
L
L
L
XX
X
ILLEGAL
Note
2
2
4
5
5
2
2
3
3
2
3
3
3
2
3
2
2
2
PRELIMINARY (February, 2008, Version 0.3)
41
AMIC Technology, Corp.