A43E16161_15 Datasheet, PDF (24/48 Pages) AMIC Technology – 1M X 16 Bit X 2 Banks Low Power Synchronous DRAM

A43E16161
* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
Active & Read/Write
0
Bank A
1
Bank B
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP
0
1
BA
Operation
0 Disable auto precharge, leave bank A active at end of burst.
1 Disable auto precharge, leave bank B active at end of burst.
0 Enable auto precharge, precharge bank A at end of burst.
1 Enable auto precharge, precharge bank B at end of burst.
4. A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP BA
0
0
0
1
1
X
Precharge
Bank A
Bank B
Both Bank
PRELIMINARY (February, 2008, Version 0.3)
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AMIC Technology, Corp.