A43P26161_15 Datasheet, PDF (30/45 Pages) AMIC Technology – 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

A43P26161
Read & Write Cycle with Auto Precharge @Burst Length=4
0
CLOCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
RBb CAa
CBb
BS1
BS0
A10/AP
RAa
RBb
WE
DQM
DQ
(CL=2)
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
Row Active
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
(D-Bank)
Auto Precharge
Start Point
(A-Bank/CL=3)
Auto Precharge
Start Point
(A-Bank/CL=2)
Write with
Auto Precharge
(D-Bank)
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode)
Auto Precharge
Start Point
(D-Bank)
: Don't care
PRELIMINARY (February, 2008, Version 1.3)
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AMIC Technology, Corp.