A43P26161_15 Datasheet, PDF (2/45 Pages) AMIC Technology – 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM

A43P26161
Preliminary
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
Features
„ Low power supply
- VDD: 2.5V VDDQ : 2.5V
„ LVCMOS compatible with multiplexed address
„ Four banks / Pulse RAS
„ MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
„ All inputs are sampled at the positive going edge of the
system clock
„ Deep Power Down Mode
„ DQM for masking
„ Auto & self refresh
„ Clock Frequency (max) : 105MHz @ CL=3 (-95)
133MHz @ CL=3 (-75)
„ 64ms refresh period (4K cycle)
„ Self refresh with programmable refresh period through
EMRS cycle
„ Programmable Power Reduction Feature by partial
array activation during Self-refresh through EMRS
cycle
„ Industrial operating temperature range: -40ºC to +85ºC
for -U series.
„ Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages.
„ Package is available to lead free (-F series)
„ All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43P26161 is 67,108,864 bits Low Power
synchronous high data rate Dynamic RAM organized as 4
X 1,048,576 words by 16 bits, fabricated with AMIC’s high
performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth, high performance memory system
applications.
Pin Configuration
„ 54 Balls CSP (8 mm x 8 mm)
Top View
54 Ball (6X9) CSP
1
2
3
7
8
9
A
VSS
DQ15 VSSQ VDDQ DQ0
VDD
B
DQ14 DQ13 VDDQ VSSQ DQ2
DQ1
C
DQ12 DQ11 VSSQ VDDQ DQ4
DQ3
D
DQ10 DQ9 VDDQ VSSQ DQ6
DQ5
E
DQ8
NC
VSS
VDD LDQM DQ7
F
UDQM CLK
CKE _{CAS RAS}
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
PRELIMINARY (February, 2008, Version 1.3)
1
AMIC Technology, Corp.