A25L010A Datasheet, PDF (21/44 Pages) AMIC Technology – 1Mbit Low Voltage, Serial Flash Memory

Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits
inside the chosen sector. Before it can be accepted, a Write
Enable (WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip
Select ( ^S ) Low, followed by the instruction code on Serial
Data Input (DIO). Chip Select ( ^S ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 13. Chip Select
( ^S ) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Sector Erase
Figure 13. Sector Erase (SE) Instruction Sequence
A25L010A Series
instruction is not executed. As soon as Chip Select ( ^S ) is
driven High, the self-timed Sector Erase cycle (whose
duration is t_SE) is initiated. While the Sector Erase cycle is in
progress, the Status Register may be read to check the value
of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is
0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is
protected by the Sector/Block Protect (SEC, TB, BP2, BP1,
BP0) bits (see table 1 and table 2.) is not executed.
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-Bit Address
DIO
23 22 21 3 2 1 0
MSB
Note: Address bits A23 to A17 are Don’t Care, for A25L010A.
(November, 2014, Version 1.5)
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AMIC Technology Corp.