AMIS-722402 Datasheet, PDF (9/15 Pages) AMI SEMICONDUCTOR – Contact Image Sensor

AMIS-722402: Contact Image Sensor
Data Sheet
8.0 Timing Requirements
Table 6 lists the timing requirements for all four resolution modes, and their associated timing diagrams are shown in Figures 4-9.
Table 6: Timing Requirements
Parameter
Symbol Min. Typ. Max.
Units
Clock (CLK) period
CLKp
330
400
2000
ns
Clock (CLK) pulse width
CLKpw
200
ns
Clock (CLK) duty cycle
Data setup time ⁽¹⁾
Data hold time ⁽¹⁾
Clock (CLK) rise time ⁽²⁾
Clock (CLK) fall time ⁽²⁾
End-of-scan (SO) rise time ⁽²⁾
End-of-scan (SO) fall time ⁽²⁾
Global start (GBST) rise time ⁽³⁾
Global start (GBST) fall time ⁽³⁾
Pixel rise time ^(4,5)
Pixel fall time ^(4,5)
50
%
Tset
20
ns
Thold
25
ns
CLKrt
70
ns
CLKft
70
ns
SOrt
50
ns
SOft
50
ns
GBSTrt
70
ns
GBSTft
70
ns
Prt
100
ns
Pft
30
ns
Notes:
1. The shift register will load on all falling CLK edges, so setup and hold times (Tset, Thold) are needed to prevent the loading of multiple start pulses. This would
occur if the GBST remains high during two fallings edges of the CLK signal. See Figure 8.
2. SI starts the register scanning and the first active pixel is read out on the 76^th clock of the CLK signal. However, when multiple sensors are sequentially scanned,
as in CIS modules, the SO from the predecessor sensor becomes the SI to the subsequent sensor, hence the SI clock = the SO clock.
3. As discussed under the third unique feature, the GBST starts the initialization process and preprocesses all sensors simultaneously in the first 75 clock cycles
before the first pixel is scanned onto the video line from the first sensor.
4. The transition between pixels does not always reach the dark offset level as shown in the timing diagrams, see Vout. The timing diagrams show the transition
doing so for illustration purposes; however a stable pixel sampling point does exist for every pixel.
5. The pixel rise time is defined as the time from when the CLK’s rising edge has reached 50 percent of its maximum amplitude to the point when a pixel has reached
90 percent of its maximum amplitude. The pixel fall time is defined as the time from when the CLK’s falling edge has reached 50 percent of its maximum amplitude
to the point when a pixel has reached 10 percent of its maximum amplitude.
Figures 4, 5, 6, and 7 show the initialization of the first sensor in relation to its subsequent cascaded sensors for all four resolution
modes. The SIC selects the first sensor to operate with 75 clock cycles of delay by connecting it to Vdd on the first sensor and to
Ground for all of the subsequent sensors. Hence the first sensor will operate with 75 inactive pixels being clocked out before its first
active pixel is clocked out.
GBST
CLK
SO
VOUT
1
2
3
72
73
74
75
76
77
78
79
1442 1443 1444 ₁₄₄₇ 1448 _{1449 1450 1451}
75 Inactive Pixels (75 Clocks)
1
2
3
4 _{1367 1368 1369 1372 1373 1374 1375 1376}
1376 Active Pixels (1376 Clocks)
Figure 4: Overall Timing Diagram for the 2400dpi Mode
AMI Semiconductor – Jan. 06, M-20499-004
9
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