AMIS-720639 Datasheet, PDF (8/10 Pages) AMI SEMICONDUCTOR – 600dpi CIS Sensor Chip

AMIS-720639: 600dpi CIS Sensor Chip
Data Sheet
Figure 6, shows the buffer amplifier configuration. The general video wave shape and timing characteristics of this circuit are discussed
in Section 6.0. Figure 4 shows the general signal wave shape and its timing relationship to the clock. Table 6 defines the symbols
used in Figure 4. This circuit is generally employed in CIS applications where the clock speeds are under 5.0MHz.
IOUT
Figure 6: Voltage Buffer Amplifier
This video line charging implementation is extensively used because of its simplicity and low cost, however, speed is limited because of
the video line capacitance. For any given video line capacitance, the rate of signal charge remains the same, creating the charging
slope. As the sampling frequency is increased, the pixel’s signal window decreases, reducing the amplitude and at very high frequency
the video sample becomes triangular in shape. This effect is especially prevalent when longer line arrays are implemented. However,
the CIS modules are cascaded structures of N Image sensors in series, forming various lengths of line arrays. It is easy to see that as N
increases, the length of the video line on the PCB increases, thus increasing the video line capacitance and making it difficult to extract
the signal, especially at high speeds.
The third circuit is desirable for high-speed application, specifically, above 5.0MHz. Again, a buffer amplifier is employed. It uses the
same buffer stage as in the second circuit. It has a positive-going output buffer amplifier, but instead of applying the video directly to
the input of the amplifier, it uses a small shunt-sensing resistor to ground (see Figure 7). In this case, a small 50Ω resistor load, low
enough in impedance to allow the image sensor to effectively see a virtual ground, is employed. This low impedance minimizes the
effect of video line capacitance. The signal is pulsed out as an impulse current. This signal current produces a fast rising signal voltage
across the resistor, then the signal decays at a slightly slower rate. At high clock rates, the time duration is short enough for the
impulse current to develop an approximated square wave voltage across the resistor (see Figure 3). Iout, the signal current across the
50Ω is exemplified as a very fast rising and falling signal voltage pulse. The advantage of this circuit is that it is a positive going output
signal, which eliminates the need for the second inverter stage. In addition, although it is not recommended for low frequency
operation, its low impedance video line lends to high-speed operation, above 5.0MHz. Accordingly, this circuit offers the advantages of
high-speed performance in addition to its cost and implementation advantages. The disadvantage to this circuit is that since it senses
the output on a 50Ω resistor, the signal-to-noise is slightly less than the circuit that stores the signal charges on the video line.
AMI Semiconductor – May 06, M-20569-001
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