AMIS-720639 Datasheet, PDF (4/10 Pages) AMI SEMICONDUCTOR – 600dpi CIS Sensor Chip

AMIS-720639: 600dpi CIS Sensor Chip
Data Sheet
3.0 Absolute Maximum Ratings
Table 3: Absolute Maximum Ratings
Parameters
Power supply voltage
Power supply current
Input clock pulse (high level)
Input clock pulse (low level)
Symbol
VDD
IDD
Vih
Vil
Maximum Rating
7.0
<3.0
Vdd + 0.5
-0.25
Units
V
ma
V
V
4.0 Environmental Ratings
Table 4: Environmental Ratings
Parameters
Operating Temperature
Operating humidity
Storage temperature
Storage humidity
Symbol
Top
Hop
Tstg
Hstg
Maximum Rating
0 to 50
10 to 85
-25 to 75
10 to 90
Units
°_C
RH %
°_C
RH %
5.0 Operating Range at Room Temperature
Table 5: Recommended Operating Conditions at Room Temperature
Parameters
Symbols
Min.
Typical
Max.
Units
Power supply
Input clock pulses high level
Input clock pulse low level
Video signal current (charge for given sample
VDD
4.5
5.0
5.5
V
Vih ⁽¹⁾
4.0
5.0
VDD
V
Vil ⁽¹⁾
0
0
0.8
V
Iout ⁽²⁾
See Note 2
time)
Clock frequency
Clock pulse duty cycle
fclk ⁽³⁾⁽⁴⁾
0.1
5.0
Dty ⁽⁵⁾
50
6.5
MHz
%
Clock pulse high durations
Integration time
Operating temperature
Tw
100
Tint ⁽⁶⁾
29.54
Top
25
nsec
µsec
50
°_C
Notes:
(1) Applies to both CP and SP.
(2) See Note 3 under Table 2.
(3) Although the clock frequency will operate the device at less than 100kHz, it is recommended that the device be operated above 500kHz. This recommendation is
for long module length, such as the A4 size with 27 sequentially cascaded sensors. The long module at low clock rates has a long scan time. This results in a long
photo integration time that generates leakage currents. The leakage currents randomly store arbitrary amounts of charges in the photo-site, contributing to the FPN
in the dark.
(4) For fclk < 5.0MHz, the clock duty cycle is typically 25 percent. But at fclk = 5.0MHz or higher a typical of 50 percent is recommended. This is to keep the die-to-
die, fixed pattern noise (FPN), to a minimum between die transitions in CIS operation.
(5) Duty cycle is the ratio of clock pulse width over the clock period.
(6) Tint at the minimum integration time is specified with a maximum clock frequency of 6.5MHz. This specification is for a single sensor. When multiple sensors are
cascaded in series, this minimum integration time increases with each additional number of sensors.
AMI Semiconductor – May 06, M-20569-001
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