PI3012A Datasheet, PDF (4/7 Pages) AMI SEMICONDUCTOR – 300DPI CIS Sensor Chip

Absolute Maximum Ratings:
Parameters
Power Supply Voltage
Power Supply Current
Input clock pulse (high level)
Input clock pulse (low level)
Operating Temperature
Operating Humidity
Storage Temperature
Storage Humidity
VDD
IDD
Vih
Vil
Top
Hop
Tstg
Hstg
Symbol
Maximum Rating
10
<2.0
Vdd + 0.5
-0.25
0 to 50
10 to 85
-25 to 75
10 to 90
Units
Volts
ma
Volts
Volts
o_C
RH %
o_C
RH %
Recommended Operating Conditions at Room Temperature
Parameters
Symbol Min. Typical Max.
Power Supply
VDD
4.5
5.0
5.5
Input clock pulses high level
Vih
2.8
5.0
VDD
Input clock pulse low level
Vil
0
0
0.8
Operating high level exposed output Iout
Clock Frequency
f
0.1
2.0
5.0
Clock pulse duty cycle
25
Clock pulse high durations
tw
0.125
Integration time
Tint
1.3
10
Operating Temperature
Top
25
50
Units
Volts
Volts
Volts
MHz
%
µsec
ms
o_C
Notes
1
1
2
3
4
4
3
Notes:
(1) Applies to both CP and SP.
(2) The output is a current that is proportional to the charges, which are integrated on the
phototransistor’s base via photon-to-electron conversion. Accordingly during read out, these
charges are discharged from the base through the transistor’s emitter proportionally to the Beta
of the phototransistor. Hence, the emitter current, that flows to the output video line, is the
signal that is proportional to the photon integrated charges. To gain the optimum performance,
the signal interfacing circuits are designed consistently with this signal process. The video
signal current is made to flow into a virtual ground, while the signal extraction circuit is made to
integrate these charges that converts these charges into the output signal voltage. The circuit
used for the converting the current charge to voltage is attached to this document as a
separate sheet.
(3) Although the clock frequency will operate the device at less than 100KHz, it is
recommended that the device be operated above 500KHz to maintain the devices performance
characteristic.
(4) The clock duty cycle typically is 25 %. However, it can operate with duty cycle as large as
50 %. This specified duty cycle is suggested because the 25 % of clock time, or the positive
time of the clock, is used in the reset process, while the remainder of the time is used inextracting
the signal during each pixel. Accordingly at low clock frequencies, it would help the
PAGE 4 OF 7 PI3012A, 6/9/99