AMIS-42665 Datasheet, PDF (4/13 Pages) AMI SEMICONDUCTOR – High-Speed Low Power CAN Transceiver

AMIS-42665 High-Speed Low Power CAN Transceiver
Data Sheet
7.0 Functional Description
7.1 Operating Modes
AMIS-42665 provides two modes of operation as illustrated in Table 3. These modes are selectable through pin STB.
Table 3: Operating Modes
Mode
Pin
STB
Low
Pin RXD
High
Normal Low
Bus dominant
Bus recessive
Standby High Wake-up request detected No wake-up request detected
7.1.1. Normal Mode
In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN
controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME.
7.1.2. Standby Mode
In standby mode both the transmitter and receiver are disabled and a very low-power differential receiver monitors the bus lines for
CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10µA. When a wake-up
request is detected by the low-power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time
period of t_BUS, the RxD pin is driven low by the transceiver to inform the controller of the wake-up request.
7.2 Split Circuit
The V_SPLIT pin is operational only in normal mode. In standby mode this pin is floating. The V_SPLIT is connected as shown in Figure 2 and
its purpose is to provide a stabilized DC voltage of 0.5 x V_CC to the bus avoiding possible steps in the common-mode signal therefore
reducing EME. These unwanted steps could be caused by an un-powered node on the network with excessive leakage current from the
bus that shifts the recessive voltage from its nominal 0.5 x V_CC voltage.
7.3 Wake-up
Once a valid wake-up (dominant state longer than t_BUS) has been received during the standby mode the RxD pin is driven low.
7.4 Over-temperature Detection
A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of
approximately 160°C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is
reduced. All other IC functions continue to operate. The transmitter off-state resets when pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
7.5 TxD Dominant Time-out Function
A TxD dominant time-out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network
communication) if pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a
negative edge on pin TxD. If the duration of the low-level on pin TxD exceeds the internal timer value t_dom, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a positive edge on pin TxD.
This TxD dominant time-out time (t_dom)defines the minimum possible bit rate to 40kBaud.
7.6 Fail Safe Features
A current-limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or
negative supply voltage, although power dissipation increases during this fault condition.
AMI Semiconductor – Rev. 3.1, April 06
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