PI3042A Datasheet, PDF (14/18 Pages) AMI SEMICONDUCTOR – Contact Image Sensor Chip

Preliminary PI3042A datasheet
Sensor’s Operational Specifications
Absolute Maximum Ratings:
Parameters
Symbol
Maximum Rating
Power Supply Voltage
VDD
10
Power Supply Current
IDD
<2.0
Input clock pulse (high level)
Vih
Vdd + 0.5
Input clock pulse (low level)
Vil
-0.25
Operating Temperature
Top
0 to 50
Operating Humidity
Hop
10 to 85
Storage Temperature
Tstg
-25 to 75
Storage Humidity
Hstg
10 to 90
Table 7. Absolute Maximum Ratings
Units
Volts
ma
Volts
Volts
o_C
RH %
o_C
RH %
Recommended Operating Conditions at Room Temperature
Parameters
Symbol Min. Typical Max.
Units
Power Supply
VDD
4.5
5.0
5.5
Volts
Input clock pulses high level
Vih ⁽¹⁾
3.0
5.0
VDD
Volts
Input clock pulse low level
Vil ⁽¹⁾
0
0
0.8
Volts
Operating high level exposed output IOUT ⁽²⁾
See note.
Clock Frequency
Fclk ⁽³⁾
0.1
2.0
5.0
MHz
Clock pulse duty cycle
Duty ⁽⁴⁾
25
%
Clock pulse high durations
tw
0.125
sec
Integration time
Tint
Operating Temperature
Top
0.864
10
ms
25
50
o_C
Table 8. Recommended Operating Condition At Room Temperature
Note (1)
(2)
(3)
(4)
Applies to both CP and SP.
The output is a current that is proportional to the charges, which are
integrated on the phototransistor’s base via photon-to-electron conversion.
For its conversion to voltage pixels see Figure 4, Video Pixel Output Structure
in section Output Circuit Of The Image Sensor.
Although the clock frequency, Fclk, will operate the device at less than
100KHz, it is recommended that the device be operated above 500KHz to
avoid complication of leakage current build-up. In applications using long CIS
module length, such as an array of image sensor > 27, increases the readout
time, i.e., increases Tint, hence, leakage current build-up occurs.
The clock duty cycle typically is normally set to 25 %. However, it can operate
with duty cycle as large as 50 %, which will allow more reset time at the
expense of video pixel readout time. At clock frequencies approaching 5.0
MHz it is recommended to use 50% duty cycle to allow more time for the
signal pixel to integrate and settle.
Page 14 of 18 Date: 09/23/05