AM29LV800B Datasheet, PDF (8/42 Pages) Advanced Micro Devices – 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV800B Device Bus Operations
DQ8–DQ15
Read
Write
Operation
Standby
CE# OE# WE# RESET#
L
LH
H
L HL
H
V_CC ±
0.3 V
X
X
V_CC ±
0.3 V
Addresses
(Note 1)
A_IN
A_IN
X
DQ0–
DQ7
D_OUT
D_IN
BYTE#
= V_IH
D_OUT
D_IN
BYTE#
= V_IL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-Z High-Z
High-Z
Output Disable
L HH
H
X
High-Z High-Z
High-Z
Reset
X XX
L
X
High-Z High-Z
High-Z
Sector Address,
Sector Protect (Note 2)
L HL
V_ID
A6 = L, A1 = H, D_IN
X
X
A0 = L
Sector Address,
Sector Unprotect (Note 2)
L HL
V_ID
A6 = H, A1 = H, D_IN
X
X
A0 = L
Temporary Sector Unprotect
X XX
V_ID
A_IN
D_IN
D_IN
High-Z
Legend:
L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 12.0 ± 0.5 V, X = Don’t Care, A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V_IH), A18:A-1 in byte mode (BYTE# = V_IL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and control-
led by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V_IL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V_IH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The
device remains enabled for read access until the com-
mand register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I_CC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
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Am29LV800B