AM70PDL127CDH Datasheet, PDF (63/127 Pages) SPANSION – Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)

ADVANCE INFORMATION
PSRAM DC CHARACTERISTICS
Recommended DC Operating Conditions (Note 1)
Item
Supply Voltage
Ground
Symbol
V_CC
V_SS
Input High Voltage
V_IH
Input Low Voltage
V_IL
Notes:
1. T_A = -40 to 85°C, otherwise specified.
2. Overshoot: V_CC + 1.0 V in case of pulse width ≤ 20 ns.
Capacitance (f= 1MHz, TA = 25°C)
Min
Typ
2.7
2.9
0
0
2.2
-
-0.3 (Note 3)
-
Max
3.1
0
V_CC + 0.3
(Note 2)
0.6
Unit
V
V
V
V
3. Undershoot: -1.0 V in case of pulse width ≤ 20 ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Input Capacitance
C_IN
Input/Output Capacitance
C_IO
Note: Capacitance is sampled, not 100% tested.
Test Condition
V_IN= 0 V
V_IO= 0 V
Min Max Unit
-
8
pF
-
10
pF
DC and Operating Characteristics
Item
Symbol
Test Conditions
Min Typ Max Unit
Input Leakage Current
I_LI
V_IN= V_SS to V_CC
-1
-
1
µs
Output Leakage Current
I_LO CS#1s= V_IH, CS2s= V_IH or WE#= V_IL, V_IO= V_SS to V_CC -1
-
1
µs
Average Operating Current
Cycle time = 1ms, 100% duty, I_IO= 0 mA,
I_CC1 CS#1s ≤ 0.2 V, CS2s ≥ V_CC ≤ 0.2 V or
V_IN ≥ V_CC-0.2 V
-
30
7
mA
I_CC2
Cycle Time = Min, I_IO = 0 mA, 100% duty, I_IO = 0 mA,
CS#1s = V_IL, CS2s = V_IH, V_IN=V_IL or V_IH
-
-
35 mA
Output Low Voltage
V_OL I_OL= 2.1 mA
-
-
0.4
V
Output High Voltage
Standby Current (CMOS)
Deep Power Down
V_OH I_OH= -1.0 mA
I_SB1
CS#1s ≥ V_CC-0.2 V, CS2s ≥ V_CC-0.2 V,
Other inputs= V_SS to V_CC
I_SBD CS2s ≤ 0.2V, Other inputs= V_SS to V_CC
2.4
-
-
V
-
-
80
µs
-
-
20
µs
Note: Typical values are tested at V_CC= 2.9 V, T_A= 25°C and not guaranteed.
November 24, 2003
Am70PDL127CDH/Am70PDL129CDH
61