AM70PDL127CDH Datasheet, PDF (60/127 Pages) SPANSION – Stacked Multi-Chip Package (MCP/XIP) Flash Memory, Data storage MirrorBit Flash, and pSRAM (XIP)

ADVANCE INFORMATION
Table 18. Write Operation Status
Standard
Mode
Erase
Suspend
Mode
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
Read
Non-Erase
Suspended Sector
Erase-Suspend-Program
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
1
No toggle
Data
DQ7#
Data
Toggle
DQ5
(Note 1)
0
0
0
Data
0
DQ3
N/A
1
N/A
DQ2
(Note 2)
No toggle
Toggle
Toggle
Data
N/A
Data
N/A
RY/BY#
0
0
1
1
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
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Am70PDL127CDH/Am70PDL129CDH
November 24, 2003