AMD-750 Datasheet, PDF (6/12 Pages) Advanced Micro Devices – Chipset

AMD-750™ Chipset Overview
23016A—August 1999
n Transaction Queues:
• Command queue (CQ)
• Memory write queue (MWQ)
• Memory read queue (MRQ)
• Probe (snoop) queue (PQ)
Integrated Memory Controller
The integrated memory controller has the following features:
n Memory Request Organizer (MRO)—Serves as a data
crossbar, determines request dependencies, and optimizes
scheduling of memory requests
n The AMD-751 system controller supports the following
concurrences:
• Processor-to-main-memory with PCI-to-main-memory
• Processor-to-main-memory with AGP-to-main-memory
• Processor-to-PCI with PCI-to-main-memory or
AGP-to-main-memory
n Memory error correcting code (ECC) support
n Supports the following DRAM:
• Up to three non-buffered PC-100 revision 1.0 SDRAM
DIMMs using 16-Mbit, 64-Mbit, and 128-Mbit technology
• 64-bit data width, plus 8-bit ECC paths
• Flexible row and column addressing
n Supports up to 768 Mbytes of memory
n Four open pages within one CS (device selected by chip
select) for one quadword
n Default two-page leapfrog policy for eight quadword
requests
n BIOS-configurable memory-timing parameters and
configuration parameters
n 3.3-V memory interface operation with no external buffers
n Four cache lines (32 quadwords) of processor-to-DRAM
posted write buffers with full read-around capability
n Concurrent DRAM writeback and read-around-write
n Burst read and write transactions
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AMD-751™ System Controller