CS5530A Datasheet, PDF (58/259 Pages) National Semiconductor (TI) – Geode CS5530A I/O Companion Multi-Function South Bridge

Revision 1.1
Resets and Clocks
Table 4-9. DCLK Configuration Register
Bit Description
F4BAR+Memory Offset 24h-27h
DOT Clock Configuration Register (R/W)
Reset Value = 00000000h
31
30
29
28:24
23
22:12
11
10
9
8
7:6
5
4:3
2:0
Note:
Feedback Reset: Reset the PLL postscaler and feedback divider. 0 = Normal operation; 1 = Reset.
A more comprehensive reset description is provided in bit 8.
Half Clock: 0 = Enable; 1 = Disable.
For odd post divisors, half clock enables the falling edge of the VCO clock to be used to generate the falling edge of the post
divider output to more closely approximate a 50% output duty cycle.
Reserved: Set to 0.
5-Bit DCLK PLL Post Divisor (PD) Value: Selects value of 1 to 31.
00000 = PD divisor of 8
00001 = PD divisor of 6
00010 = PD divisor of 18
00011 = PD divisor of 4
00100 = PD divisor of 12
00101 = PD divisor of 16
00110 = PD divisor of 24
00111 = PD divisor of 2
01000 = PD divisor of 10
01001 = PD divisor of 20
01010 = PD divisor of 14
01011 = PD divisor of 26
01100 = PD divisor of 22
01101 = PD divisor of 28
01110 = PD divisor of 30
01111 = PD divisor of 1*
10000 = PD divisor of 9
10001 = PD divisor of 7
10010 = PD divisor of 19
10011 = PD divisor of 5
10100 = PD divisor of 13
10101 = PD divisor of 17
10110 = PD divisor of 25
10111 = PD divisor of 3
11000 = PD divisor of 11
11001 = PD divisor of 21
11010 = PD divisor of 15
11011 = PD divisor of 27
11100 = PD divisor of 23
11101 = PD divisor of 29
11110 = PD divisor of 31
11111 = Reserved
*See bit 11 description.
Plus 1 (+1): Adds 1 or 0 to FD (DCLK PLL VCO Feedback Divisor) parameter in equation (see Note).
0 = Add 0 to FD; 1 = Add 1 to FD.
N: This bit represents “N” in the equation (see Note). It is used to solve the value of FD (DCLK PLL VCO feedback divisor).
N can be a value of 1 to 400. For all values of N, refer to Table 4-10 on page 59.
CLK_ON: 0 = PLL disable; 1 = PLL enable. If PD = 1 (i.e., bits [28:24] = 01111) the PLL is always enabled and cannot be
disabled by this bit.
DOT Clock Select: 0 = DCLK; 1 = TV_CLK.
Reserved: Set to 0
Bypass PLL: Connects the input of the PLL directly to the output of the PLL. 0 = Normal Operation; 1 = Bypass PLL.
If this bit is set to 1, the input of the PLL bypasses the PLL and resets the VCO control voltage, which in turn powers down
the PLL. Allow 0.5 ms for the control voltage to be driven to 0V.
Reserved: Set to 0.
Reserved (Read Only): Write as read
Reserved: Set to 0.
PLL Input Divide (ID) Value: Selects value of 2 to 9 (see Note).
000 = ID divisor of 2
010 = ID divisor of 4
100 = ID divisor of 6
110 = ID divisor of 8
001 = ID divisor of 3
011 = ID divisor of 5
101 = ID divisor of 7
111 = ID divisor of 9
To calculate DCLK output frequency:
Equation #1: DCLK = [CLK_14MHZ * FD] ÷ [PD *ID]
Condition: 140 MHz < [DCLK * PD] < 300 MHz
Where:
CLK_14MHZ is pin P24
FD is derived from N see equation #2 and #3
PD is derived from bits [28:24]
ID is derived from bits [2:0]
Equation #2: If FD is an odd number then: FD = 2*N +1
Equation #3: If FD is an even number then: FD = 2*N +0
Where: N is derived from bits [22:12]
+1 is achieved by setting bit 23 to 1.
+0 is achieved by clearing bit 23 to 0.
58
AMD Geode™ CS5530A Companion Device Data Book