CS5530A Datasheet, PDF (48/259 Pages) National Semiconductor (TI) – Geode CS5530A I/O Companion Multi-Function South Bridge

Revision 1.1
4.1 Processor Interface
The CS5530A interface to the GX1 processor consists of
seven miscellaneous connections, the PCI bus interface
signals, plus the display controller connections. Figure 4-1
shows the interface requirements. Note that the PC/AT leg-
acy pins NMI, WM_RST, and A20M are all virtual functions
executed in SMM (System Management Mode) by the
BIOS.
• PSERIAL is a one-way serial bus from the processor to
the CS5530A used to communicate power management
states and VSYNC information for VGA emulation.
• IRQ13 is an input from the processor indicating that a
floating point error was detected and that INTR should
be asserted.
• INTR is the level output from the integrated 8259 PICs
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
• SMI# is a level-sensitive interrupt to the processor that
can be configured to assert on a number of different
system events. After an SMI# assertion, SMM is entered
and program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
• SUSP# and SUSPA# are handshake pins for imple-
menting CPU Clock Stop and clock throttling.
• CPU_RST resets the CPU and is asserted for approxi-
mately 9 ms after the negation of POR#.
• PCI bus interface signals.
• Display subsystem interface connections.
Processor Interface
AMD Geode™
CS5530A
Companion Device
PSERIAL
IRQ13
INTR
SMI#
SUSP#
SUSPA#
CPU_RST
AMD Geode™
GX1
Processor
SERIALP
IRQ13
INTR
SMI#
SUSP#
SUSPA#
RESET
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ#
GNT#
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ0#
GNT0#
PCLK
DCLK
HSYNC
VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
PIXEL[23:0]
Note
PCLK
DCLK
CRT_HSYNC
CRT_VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
PIXEL[17:0]
Note: Refer to Figure 4-3 on page 50 for correct
interconnection of PIXEL lines with the processor.
Figure 4-1. Processor Signal Connections
48
AMD Geode™ CS5530A Companion Device Data Book