AM50DL128CG Datasheet, PDF (51/63 Pages) SPANSION – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

PRELIMINARY
FLASH AC CHARACTERISTICS
Alternate CE#f Controlled Erase and Program Operations
Parameter
JEDEC
Std
Description
t_AVAV
t_AVWL
t_ELAX
t_DVEH
t_EHDX
t_GHEL
t_WC
t_AS
t_AH
t_DS
t_DH
t_GHEL
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write
(OE# High to WE# Low)
t_WLEL
t_EHWH
t_ELEH
t_EHEL
t_WHWH1
t_WS
t_WH
t_CP
t_CPH
t_WHWH1
WE# Setup Time
WE# Hold Time
CE#f Pulse Width
CE#f Pulse Width High
Programming Operation
(Note 2)
Byte
Word
t_WHWH1
t_WHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
t_WHWH2
t_WHWH2 Sector Erase Operation (Note 2)
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
3. CE#f refers to active flash device being addressed (either CE#f1 or CE#f2).
Speed
70
85 Unit
Min
70
85
ns
Min
0
ns
Min
40
45
ns
Min
40
45
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
40
45
ns
Min
30
ns
Typ
5
µs
Typ
7
Typ
4
µs
Typ
0.4
sec
50
Am50DL128CG
November 7, 2002