AM50DL128CG Datasheet, PDF (2/63 Pages) SPANSION – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

PRELIMINARY
Am50DL128CG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Two Am29DL640G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation
Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
■ High performance
— Access time as fast as 70 ns
■ Package
— 88-Ball FBGA
■ Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■ Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■ Flexible Bank architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
■ Manufactured on 0.17 µm process technology
■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
— Customer lockable: Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■ Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■ Boot sectors
— Top and bottom boot sectors in the same device
■ Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
■ High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
■ Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■ Minimum 1 million write cycles guaranteed per sector
■ 20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■ Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■ Supports Common Flash Memory Interface (CFI)
■ Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■ Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
■ Any combination of sectors can be erased
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
■ Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
■ WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1, 140, and
141, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
■ Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
pSRAM Features
■ Power dissipation
— Operating: 50 mA maximum
— Standby: 100 µA maximum
— Deep power-down standby: 5 µA
■ CE1s# and CE2s Chip Select
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 2.7 to 3.3 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■ 8-word page mode access
This document contains information on a product under development at Advanced Micro Devices. The information
Publication# 26880 Rev: A Amendment/+2
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
Issue Date: November 7, 2002
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.