AM79C978 Datasheet, PDF (37/261 Pages) Advanced Micro Devices – Single-Chip 1/10 Mbps PCI Home Networking Controller

is a single function device. AD[31:11] are “don't cares.”
See Table 6.
Table 6. Slave Configuration Transfers
AD31
AD11
Don’t care
AD10
AD8
Don’t care
AD7
AD2
DWord
Index
AD1 AD0
0
0
The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, and 32-bit trans-
fers are supported. DEVSEL is asserted two clock cy-
cles after the host has asserted FRAME. All
configuration cycles are of fixed length. The
Am79C978 controller will assert TRDY on the third
clock of the data phase.
The Am79C978 controller does not support burst trans-
fers for access to configuration space. When the host
keeps FRAME asserted for a second data phase, the
Am79C978 controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C978 controller will terminate the access on the
PCI bus with a disconnect/retry response.
The Am79C978 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C978 controller
is capable of detecting a configuration cycle even when
its address phase immediately follows the data phase
of a transaction to a different target without any idle
state in-between. There will be no contention on the
DEVSEL, TRDY, and STOP signals, since the
Am79C978 controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
Slave I/O Transfers
After the Am79C978 controller is configured as an I/O
device by setting IOEN (for regular I/O mode) or
MEMEN (for memory mapped I/O mode) in the PCI
Command register, it starts monitoring the PCI bus for
access to its CSR, BCR, or EEPROM locations. If con-
figured for regular I/O mode, the Am79C978 controller
will look for an address that falls within its 32 bytes of I/
O address space (starting from the I/O base address).
The Am79C978 controller asserts DEVSEL if it detects
an address match and the access is an I/O cycle. If
configured for memory mapped I/O mode, the
Am79C978 controller will look for an address that falls
within its 32 bytes of memory address space (starting
from the memory mapped I/O base address). The
Am79C978 controller asserts DEVSEL if it detects an
address match and the access is a memory cycle.
DEVSEL is asserted two clock cycles after the host has
asserted FRAME. See Figure 3 and Figure 4.
The Am79C978 controller will not assert DEVSEL if it
detects an address match and the PCI command is not
of the correct type. In memory mapped I/O mode, the
Am79C978 controller aliases all accesses to the I/O re-
sources of the command types Memory Read Multiple
and Memory Read Line to the basic Memory Read com-
mand. All accesses of the type Memory Write and In-
validate are aliased to the basic Memory Write
command. Eight-bit, 16-bit, and 32-bit non-burst trans-
actions are supported. The Am79C978 controller de-
codes all 32 address lines to determine which I/O
resource is accessed.
The typical number of wait states added to a slave I/O
or memory mapped I/O read or write access on the part
of the Am79C978 controller is six to seven clock cycles,
depending upon the relative phases of the internal Buff-
er Management Unit clock and the CLK signal, since
the internal Buffer Management Unit clock is a divide-
by-two version of the CLK signal.
The Am79C978 controller does not support burst trans-
fers for access to its I/O resources. When the host keeps
FRAME asserted for a second data phase, the
Am79C978 controller will disconnect the transfer.
The Am79C978 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C978 controller
is capable of detecting an I/O or a memory-mapped I/
O cycle even when its address phase immediately fol-
lows the data phase of a transaction to a different target,
without any idle state in-between. There will be no con-
tention on the DEVSEL, TRDY, and STOP signals, since
the Am79C978 controller asserts DEVSEL on the sec-
ond clock after FRAME is asserted (medium timing).
See Figure 5 and Figure 6.
Am79C978
37