AM79C978 Datasheet, PDF (156/261 Pages) Advanced Micro Devices – Single-Chip 1/10 Mbps PCI Home Networking Controller

This bit is always read/write ac-
cessible. IOBASEU is not affect-
ed by S_RESET or STOP.
BCR18: Burst and Bus Control Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-12 ROMTMG
Expansion ROM Timing. The val-
ue of ROMTMG is used to tune
the timing for all EBDATA
(BCR30) accesses to Flash/
EPROM as well as all Expansion
ROM accesses to Flash/EPROM.
ROMTMG, during read opera-
tions, defines the time from when
the Am79C978 controller drives
the lower 8 or 16 bits of the Ex-
pansion Bus Address bus to
when the Am79C978 controller
latches in the data on the 8 or 16
bits of the Expansion Bus Data
inputs. ROMTMG, during write
operations, defines the time from
when the Am79C978 controller
drives the lower 8 or 16 bits of the
Expansion Bus Data to when the
EBWE and EROMCS deassert.
The register value specifies the
time in number of clock cycles +1
according to Table 36.
Table 36. ROMTNG Programming Values
ROMTMG (bits 15-12) No. of Expansion Bus Cycles
1h<=n <=Fh
n+1
Note: Programming ROMTNG
with a value of 0 is not permitted.
The access time for the Expan-
sion ROM or the EBDATA
(BCR30) device (t_ACC) during
read operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA_EBA[7:0]
outputs (tv_A_D) and by subtract-
ing the input to clock setup time
for the EBD[7:0] inputs (ts_D)
from the time defined by ROMT-
MG:
t_ACC = ROMTMG * CLK period
*CLK_FAC - (tv_A_D) + (ts_D)
The access time for the Expan-
sion ROM or for the EBDATA
(BCR30) device (t_ACC) during
write operations can be calculat-
ed by subtracting the clock to out-
put delay for the EBUA EBA[7:0]
outputs (tv_A_D) and by adding
the input to clock setup time for
Flash/EPRO inputs (ts_D) from
the time defined by ROMTMG.
t_ACC = ROMTMG * CLK period *
CLK_FAC - (tv_A_D) - (ts_D)
For an adapter card application,
the value used for clock period
should be 30 ns to guarantee cor-
rect interface timing at the maxi-
mum clock frequency of 33 MHz.
These bits are read accessible al-
ways; write accessible only when
the STOP bit is set. ROMTMG is
set to the value of 1001b by
H_RESET and is not affected by
S_RESET or STOP. The default
value allows using an Expansion
ROM with an access time of 250
ns in a system with a maximum
clock frequency of 33 MHz.
11 NOUFLO No Underflow on Transmit. When
the NOUFLO bit is set to 1, the
Am79C978 controller will not start
transmitting the preamble for a
packet until the Transmit Start
Point (CSR80, bits 10-11) re-
quirement (except when XMTSP
= 3h, Full Packet has no meaning
when NOUFLO is set to 1) has
been met and the complete pack-
et has been DMA’d into the
Am79C978 controller. The com-
plete packet may reside in any
combination of the Bus Transmit
FIFO, the SRAM, and the MAC
Transmit FIFO as long as enough
of the packet is in the MAC Trans-
mit FIFO to meet the Transmit
Start Point requirement. When
the NOUFLO bit is cleared to 0,
the Transmit Start Point is the
only restriction on when preamble
transmission begins for transmit
packets.
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Am79C978