AM79C971 Datasheet, PDF (255/265 Pages) Advanced Micro Devices – PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Status: No current plan to fix this erratum.
10) Symptom: When the device is connected to certain repeaters and hubs, there have been reports of receiving
corrupted data and bad packets. The hubs and repeaters that are used when these problems occur do not
comply with the IEEE 802.3 specification. Specifically they do not comply with the following tolerance: +/- 100
PPM. The problem is aggravated due to the fact that the device does not flag any error message as a result
of this. In addition the transfers corrupted packets and continues the network activity. The received packets
are corrupted but the CRC error bit does not get set.
Implications: a) In situations where there is no upper-layer protocol to detect the error, there is a possibility
that data may be corrupted when the device is used in conjunction with a non-IEEE 802.3 compliant hub or
repeater. b) In situations where the upper layer protocol detects the error (which is the most common situation
there may be some degradation in network performance. There is also a possibility of failure of the link or an
inability to maintain link status.
Workaround: It is suggested to adhere to IEEE compliant hubs and repeaters. This will avoid the circum-
stances that may compromise data integrity and or contribute to degradation of network performance
Status: There are no planned modifications for the device. However, modifications have been implemented
in later devices in the PCnet family, such that they can tolerate non-compliant IEEE 803.2 repeaters and hub.
11) Symptom: When the RCVME bit in the LED registers (BCR4-7) is set, the LED output drives for one clock
cycle, or longer if the pulse stretcher is on, due to reception of any packet. The expected behavior is that this
LED should be on only when there is an address match
Implications: LED output will drive every time there is an incoming packet on the wire, even when there is no
address match.
Workaround: None
Status: No current plan to fix this erratum.
12) Symptom: Setting the DRCVBC bit (CSR15, bit 14) does not prevent the reception of broadcast packets when
the LADRF[47 (CSR10, bit 15) is set.
Implications: Broadcast packets will be received when the user wants them excluded as a Logical packet.
Extra packet processing will be required.
Workaround: None
Status: No current plan to fix this erratum.
13) Symptom: Configuration Space Vendor ID (VID) Register can not a have a value other than 0x1022.
Implications: The Configuration Space VID is programmed indirectly through the BCR35. If any value other
than 0x1022 is programmed in BCR35 either through software or thorough the EEPROM, the BCR35 will have
the correct data but the VID register will have a corrupted value.
Workaround: Use only a value of 0x1022
Status: No current plan to fix this erratum.
14) Symptom: When using the advance parity mode, the occurrence of parity error in the last transfer of descrip-
tor DMA write does not stop the chip as indicated in the data sheet.
Implication: If customized or proprietary software relies on the chip to stop due to parity error in the advanced
parity mode, then it is possible (though highly unlikely in a typical system) to get corrupted data in descriptors.
PCnet software drivers do rely on the chip to stop the device upon parity error.
Workaround: Use the interrupt generated by the SINT as an indicator for parity error.
Status: No current plan to fix this erratum.
15) Symptom: When using buffer (descriptor) chaining for transmit packets, BUFF errors are reported under cer-
tain conditions.
Implication: Transmit packets associated with this condition are truncated.
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