AM79C971 Datasheet, PDF (161/265 Pages) Advanced Micro Devices – PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

PRELIMINARY
13 LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be dis-
abled. When LEDDIS has the val-
ue 0, then the LED output value
will be governed by the LEDOUT
and LEDPOL values.
Read/Write accessible always.
LEDDIS is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
12 100E
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C971 controller is
operating at 100 Mbps mode. The
indication is valid with both the in-
ternal and external PHYs.
9
Read/Write accessible always.
100E is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
MPSE
11 MIISE
Media Independent Interface Se-
lected Enable. Indicates when the
MII interface is selected. This will
be set when either the Manage-
ment Port State Machine is se-
lecting the MII or when ASEL
(BCR2, bit1) is disabled and 8
PORTSEL (CSR15, bits 8-7) se-
lects the MII. This could control
relays to switch in and out appro-
priate filters or could control an
external PHY when sharing an
RJ45 connector.
FDLSE
Read/Write accessible always.
MIISE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
10 DXCVRCTL DXCVR Control. When the AUI
interface is the active network
port, DXCVRCTL controls the as-
sertion of the LED3 output. The
polarity of the asserted state is
controlled by the LEDPOL bit
(BCR4, bit 14). The LED3 pin can
be used to control a DC-to-DC
converter in applications that
want to connect a 10BASE2
MAU, as well as a standard DB15
AUI connector to the Am79C971
AUI port. When DXCVRCTL is
set to 1, the LED3 output will be
asserted. This could be used to
enable a DC-to-DC converter for
10BASE2 MAUs (assuming the
enable input of the DC-to-DC
converter is active high and LED-
POL is cleared to 0). When DX-
CVRCTL is cleared to 0, the
LED3 output will be deasserted.
This would power down the DC-
to-DC converter. When the
10BASE-T interface is the active
network port, the DXCVR output
is always deasserted.
Read/Write accessible always.
DXCVRCTL is cleared by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when magic frame
mode is enabled and a magic
frame is detected on the network.
Read/Write accessible always.
MPSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LED-
OUT signal when the Am79C971
controller is functioning in a Link
Pass state and full-duplex opera-
tion is enabled. When the
Am79C971 controller is not func-
tioning in a Link Pass state with
full-duplex operation being en-
abled, a value of 0 is passed to
the LEDOUT signal.
When the 10BASE-T port is ac-
tive, a value of 1 is passed to the
LEDOUT signal whenever the
Link Test Function (described in
the T-MAU section) detects a
Link Pass state and the FDEN
(BCR9, bit 0) bit is set. When the
AUI port is active, a value of 1 is
passed to the LEDOUT signal
whenever full-duplex operation
on the AUI port is enabled (both
Am79C971
161