AM30LV0064D Datasheet, PDF (21/41 Pages) Advanced Micro Devices – 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology

After the command cycle, three address cycles are
used to input the starting address for the Input Data
operation. Upon the rising edge of the final WE# pulse,
between 1 and 528 bytes of information can be loaded
into the Data Register with consecutive 50 ns WE#
pulses. Each WE# pulse will automatically advance
the Data Register address pointer by one. If additional
write pulses are issued after the last address has been
written (511 if SE# is high or 527 if SE# is low), the
Data Register address pointer will wrap around to 0. If
additional WE# pulses are issued, the device will con-
tinue to store information into the Data Register until a
new command is issued.
The Spare Area Enable input (SE#) must be low by
the time address 510 is accessed in order to load in-
formation into the last 16 bytes of the Data Register. If
the SE# input is high, the Data Register address will
advance to address 511. If the SE# input is low, the
column address will advance to address 527. This al-
lows information that needs to be programmed into the
Spare Area of the page to be loaded into the Data Reg-
isters properly. Please refer to Figure 8 for the simplified
timing diagram for Input Data and Page Program.
Page Program (10h)
The Page Program command sequence is issued after
the Input Data operation has loaded the proper data in
the Data Registers. Upon the rising edge of the command
cycle WE# pulse, this operation typically transfers in-
formation from the Data Registers to the Flash array in
200 µs or less, and the Flash device will appear busy
during the data transfer operation. The RY/BY# signal
or the status register may be used to monitor comple-
tion of the data transfer. Only the Reset and Read
Status commands are valid during the period that the
device is busy.
Only those bytes loaded with the Input Data command
sequence will be programmed in the Flash array. This
allows partial page programming to be performed as
needed. If no bytes were loaded into the Data Regis-
ter, or if the Page Program command is issued without
the Input Data command being performed, no program
operation will occur. Unless ECC has been imple-
mented, a given page may not be reprogrammed
without an intervening erase operation being per-
formed on the block that contains that page. After
programming a page, the status register bit I/O0
should be checked to verify that the program operation
completed properly.
The Spare Area Enable input (SE#) must be low in
order to program information into the last 16 bytes of
the page that is selected for programming. If the SE#
input is high, the Spare Area will not be programmed.
Please refer to Figure 8 for the simplified timing diagram
for Input Data and Page Program and to Figure 9 for a
flow chart describing the device program procedure.
CE#
CLE
ALE
WE#
RE#
I/O7-0
Input Data (80h)
CMD
Start Address
Page Program (10h)
Write Page Data (and Spare Area if Required)
CMD
SE#
Low to Write Spare Area
RY/BY#
Notes:
1. CE# is don’t care in between WE# and RE# transitions.
2. Falling edge of CE# to valid data must be >45 ns.
3. ALE must remain high for entire address latch operation; no transitions allowed.
Figure 8. Input Data and Page Program
Page Program
Am30LV0064D
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