AM29LV128MH_07 Datasheet, PDF (12/66 Pages) Advanced Micro Devices – 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control

DATA SHEET
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V_IL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V_IH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. See
the table, See “Read-Only Operations” on page 47 for
timing specifications and Figure 14 for the timing dia-
gram. See the table in “DC Characteristics” on
page 45 for the active current specification on reading
array data.
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is
selected by the higher address bits A(max)–A2. Ad-
dress bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an
asynchronous operation; the microprocessor supplies
the specific word location.
The random or initial page access is equal to t_ACC or
t_CE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to t_PACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is t_ACC or t_CE. Fast page mode ac-
cesses are obtained by keeping the “read-page ad-
dresses” constant and changing the “intra-read page”
addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V_IL, and OE# to V_IH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word Program Command Sequence” section has de-
tails on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
See the table in “DC Characteristics” on page 45 for
the active current specification for the write mode. “AC
Characteristics” on page 47 contains timing specifica-
tion tables and timing diagrams for write operations.
Write Buffer
Write Buffer Programming allows the system write to a
maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming
time than the standard programming algorithms. See
“Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts V_HH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sector
groups, and uses the higher voltage on the pin to re-
duce the time required for program operations. The
system would use a two-cycle program command se-
quence as required by the Unlock Bypass mode. Re-
moving V_HH from the WP#/ACC pin returns the device
to normal operation. Note that the WP#/ACC pin must
not be at V_HH for operations other than accelerated
programming, or device damage may result. WP# has
an internal pullup; when unconnected, WP# is at V_IH.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. See “Autoselect Mode” on page 20 and
“Autoselect Command Sequence” on page 29 for
more information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V_IO ± 0.3 V.
(Note that this is a more restricted voltage range than
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Am29LV128MH/L
25270C7 January 31, 2007