AM29PDL129H Datasheet, PDF (11/49 Pages) SPANSION – 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control and Dual chip Enable

DEVICE BUS OPERATIONS
Table 1. Am29PDL129H Device Bus Operations
Read
Operation
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect (High
Voltage)
CE1#
L
H
L
H
V_IO±
0.3 V
L
X
X
CE2#
H
L
H
L
V_IO ±
0.3 V
L
X
X
OE#
L
H
X
H
X
X
WE# RESET# WP#/ACC
H
H
X
L
H
X
(Note 2)
X
V_IO ±
0.3 V
X
H
H
X
X
L
X
X
V_ID
X
Addresses
(A21–A0)
A_IN
A_IN
X
X
X
A_IN
DQ15–
DQ0
D_OUT
D_IN
High-Z
High-Z
High-Z
D_IN
Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID = 11.5–12.5 V, V_HH = 8.5–9.5 V, X = Don’t Care, SA = Sector Address,
A_IN = Address In, D_IN = Data In, D_OUT = Data Out
Notes:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. .
2. WP#/ACC must be high when writing to sectors SA1-133, SA1-134, SA2-0, or SA2-1.
Random Read (Non-Page Read)
Address access time (t_ACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t_CE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least t_ACC–t_OE time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. Address bits A21–
A3 select an 8-word page, and address bits A2–A0 se-
lect a specific work within that page. This is an asyn-
chronous operation with the microprocessor supplying
the specific word location.
The random or initial page access is t_ACC or t_CE and
subsequent page read accesses (as long as the loca-
tions specified by the microprocessor fall within that
page) are t_PACC. When CE1# and CE2# are deas-
serted (CE1#=CE2#=V_IH), the reassertion of CE1# or
CE2# for subsequent access has access time of t_ACC
or t_CE. Here again, CE1#/CE2# selects the device and
OE# is the output control and should be used to gate
data to the output inputs if the device is selected. Fast
page mode accesses are obtained by keeping A21–
A3 constant and changing A2 to A0 to select the spe-
cific word within that page.
Table 2. Page Select
Word
A2
A1
A0
Word 0
0
0
0
Word 1
0
0
1
Word 2
0
1
0
Word 3
0
1
1
Word 4
1
0
0
Word 5
1
0
1
Word 6
1
1
0
Word 7
1
1
1
Simultaneous Operation
In addition to the conventional features (read, pro-
gram, erase-suspend read, and erase-suspend pro-
gram), the device is capable of reading data from one
bank of memory while a program or erase operation is
in progress in another bank of memory (simultaneous
operation), The bank can be selected by bank ad-
dresses (A21–A20) with zero latency.
The simultaneous operation can execute multi-func-
tion mode in the same bank.
November 2, 2005
Am29PDL129H
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