AM79C978A Datasheet, PDF (109/256 Pages) Advanced Micro Devices – Single-Chip 1/10 Mbps PCI Home Networking Controller

DWIO mode). The RDP access is a read access, and
since RAP has just been loaded with the value of 0004h,
the RDP read will yield the contents of CSR4. A read of
the BDP at this time (offset of 16h when WIO mode has
been selected, 1Ch when DWIO mode has been select-
14
RES
ed) will yield the contents of BCR4, since the RAP is
used as the pointer into both BDP and RDP space.
RAP: Register Address Port
Bit Name
Description
13 CERR
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8 RES
Reserved locations. Read and
written as zeros.
7-0 RAP
Register Address Port. The
value of these 8 bits deter-
mines which CSR or BCR will
be accessed when an I/O ac-
cess to the RDP or BDP port,
respectively, is performed.
A write access to undefined CSR
or BCR locations may cause un-
expected reprogramming of the
Am79C978A control registers. A
read access will yield undefined
values.
These bits are always read/write
accessible. RAP is cleared by
H_RESET or S_RESET and is un-
affected by setting the STOP bit.
Control and Status Registers (CSRs)
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
12
MISS
that is read or written during an RDP access will depend
upon the current setting of the RAP. RAP serves as a
pointer into the CSR space.
CSR0: Controller Status and Control Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit Name
Description
31-16 RES
15 ERR
Reserved locations. Written as
zeros and read as undefined.
Error. Error is set by the OR of
CERR, MISS, and MERR. ERR
remains set as long as any of the
error flags are true.
This bit is always read accessi-
ble only. Write operations are
ignored.
Reserved locations. This bit is al-
ways read/write accessible.
Read returns zero.
Collision Error. Collision Error is
set by the Am79C978A controller
when the device operates in half-
duplex mode and the collision in-
puts to the GPSI port fail to acti-
vate within 20 network bit times
after the chip terminates trans-
mission (SQE Test). This feature
is a transceiver test feature.
CERR reporting is disabled when
the GPSI port is active and the
Am79C978A controller operates
in full-duplex mode.
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
half-duplex 10BASE-T PHY.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the
ERR bit.
This bit is always read/write ac-
cessible. CERR is cleared by the
host by writing a 1. Writing a 0
has no effect. CERR is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
Missed Frame. Missed Frame is
set by the Am79C978A controller
when it has lost an incoming re-
ceive frame resulting from a Re-
ceive Descriptor not being
available. This bit is the only im-
mediate indication that receive
data has been lost since there is
no current receive descriptor.
The Missed Frame Counter
(CSR112) also increments each
time a receive frame is missed.
When MISS is set, INTA is as-
serted if IENA is 1 and the mask
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
bit, regardless of the settings of
IENA and MISSM.
Am79C978A
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