AM79C978A Datasheet, PDF (1/256 Pages) Advanced Micro Devices – Single-Chip 1/10 Mbps PCI Home Networking Controller

Am79C978A
PCnet™- Home
Single-Chip 1/10 Mbps PCI Home Networking Controller
DISTINCTIVE CHARACTERISTICS
n Fully integrated 1 Mbps HomePNA Physical Layer
(PHY) as defined by Home Phoneline Networking
Alliance (HomePNA) specification 1.1
— Optimized for home networking applications
over ordinary copper telephone wire
— In-band control features
n Adjustable power and speed levels
n 32 bits of reserved in-band messaging
piggybacked on Ethernet packet
— Register programmable features
n Power control
n Performance registers
n Speed control
n Major frame timing parameters programmable:
ISBI, AID ISBI, pulse width, inter-symbol time
n Fully integrated 10 Mbps PHY interface
— Comprehensive Auto-Negotiation
implementation
— Full-duplex capability
— Optimized for 10BASE-T applications
n Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
— 32-bit glueless PCI host interface
— Supports PCI clock frequency from DC to
33 MHz independent of network clock
— Supports network operation with PCI clock
from 15 MHz to 33 MHz
— High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
— PCI draft specification revision 2.2 compliant
— Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
— Supports both PCI 5.0-V and 3.3-V
signaling environments
— Plug and Play compatible
— Supports an unlimited PCI burst length
— Big endian and little endian byte
alignments supported
— Implements optional PCI power management
event (PME) pin
n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 Ethernet standard
n Compliant with HomePNA specification 1.1
n Media Independent Interface (MII) for
connecting external 10/100 Mbps transceivers
— IEEE 802.3u compliant MII
— Intelligent Auto-Poll™ external PHY status
monitor and interrupt
— Supports both auto-negotiable and non-
auto-negotiable external PHYs
— Supports 10BASE-T, 100BASETX/FX,
100BASET4, and 100BASET2 IEEE 802.3
compliant MII PHYs at full-duplex or half-
duplex
n Full-duplex operation supported on the MII port
with independent Transmit (TX) and Receive
(RX) channels
n Supports PC98/PC99 and Net PC specifications
— Implements full OnNow features including
pattern matching and link status wake-up
events
— Implements Magic Packet™ mode
— Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
— Supports PCI Bus Power Management
Interface specification revision 1.1
— Supports Advanced Configuration and Power
Interface (ACPI) specification version 1.0
— Supports Network Device Class Power
Management specification version 1.0a
n Independent internal TX and RX FIFOs
— Programmable FIFO watermarks for both TX
and RX operations
Publication# 22399 Rev: C Amendment/0
Issue Date: January 2000
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