DS42585 Datasheet, PDF (1/58 Pages) Advanced Micro Devices – Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

PRELIMINARY
DS42585
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL324D Bottom Boot 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
s Power supply voltage of 2.7 to 3.3 volt
s High performance
— 85 ns maximum access time
s Package
— 73-Ball FBGA
s Operating Temperature
— –25°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
s Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
s Secured Silicon (SecSi) Sector: Extra 64 KByte sector
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
— Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
s Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
s Bottom boot block
s Manufactured on 0.23 µm process technology
s Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
s High performance
— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate function
s Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s Minimum 1 million write cycles guaranteed per sector
s 20 Year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
s Data Management Software (DMS)
— AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
— Eases sector erase limitations
s Supports Common Flash Memory Interface (CFI)
s Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in same
bank
s Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
s Any combination of sectors can be erased
s Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
s Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
reading array data
s WP#/ACC input pin
— Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
s Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
SRAM Features
s Power dissipation
— Operating: 50 mA maximum
— Standby: 7 µA maximum
s CE1s# and CE2s Chip Select
s Power down features using CE1s# and CE2s
s Data retention supply voltage: 1.5 to 3.3 volt
s Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
This document contains information on a product under development at Advanced Micro Devices. The information
Publication# 25032 Rev: A Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
Issue Date: May 22, 2001
product without notice.
Refer to AMD’s Website (www.amd.com) for the latest information.