AM29F800T Datasheet, PDF (1/41 Pages) Advanced Micro Devices – 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory

PRELIMINARY
Am29F800T/Am29F800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS
5.0 Volt-only, Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s Package options
— 44-pin SO
— 48-pin TSOP
s Minimum 100,000 write/erase cycles guaranteed
s High performance
— 70 ns maximum access time
s Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
s Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
s Embedded Erase Algorithm
— Automatically pre-programs and erases the chip
or any sector
GENERAL DESCRIPTION
The Am29F800 is an 8 Mbit, 5.0 Volt-only Flash mem-
ory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase capability, the 8 Mbits
of data are divided into 19 sectors as follows: one 16
Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte.
Eight bits of data appear on DQ0–DQ7 in byte mode; in
word mode 16 bits appear on DQ0–DQ15. The
Am29F800 is offered in 44-pin SO and 48-pin TSOP
packages. This device is designed to be programmed
in-system with the standard system 5.0 Volt V_CC sup-
ply. A V_PP of 12.0 volts is not required for program or
erase operations. The device can also be programmed
in standard EPROM programmers.
8/18/97
s Embedded Program Algorithm
— Automatically programs and verifies data at
specified address
s Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
s Erase Suspend/Resume
— Supports reading data from or programming
data to a sector not being erased
s Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
s Enhanced power management for standby
mode
— 1 µA typical standby current
s Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
s Hardware RESET pin
— Resets internal state machine to the read mode
The standard Am29F800 offers access times of 70 ns, 90
ns, 120 ns, and 150 ns, allowing high-speed micropro-
cessors to operate without wait states. To eliminate bus
contention, the device has separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
The Am29F800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and program circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
Publication# 20375 Rev: C Amendment/+1
Issue Date: August 1997