AM29DL400B Datasheet, PDF (1/42 Pages) Advanced Micro Devices – 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

PRELIMINARY
Am29DL400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
s Simultaneous Read/Write operations
— Host system can program or erase in one bank,
then immediately and simultaneously read from
the other bank
— Zero latency between read and write operations
— Read-while-erase
— Read-while-program
s Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
s Manufactured on 0.35 µm process technology
s High performance
— Access times as fast as 70 ns
s Low current consumption (typical values
at 5 MHz)
— 7 mA active read current
— 21 mA active read-while-program or read-while-
erase current
— 17 mA active program-while-erase-suspended
current
— 200 nA in standby mode
— 200 nA in automatic sleep mode
— Standard t_CE chip enable access time applies to
transition from automatic sleep mode to active
mode
s Flexible sector architecture
— Two 16 Kword, two 8 Kword, four 4 Kword, and
six 32 Kword sectors in word mode
— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and
six 64 Kbyte sectors in byte mode
— Any combination of sectors can be erased
— Supports full chip erase
s Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
s Sector protection
— Hardware method of locking a sector to prevent
any program or erase operation within that
sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s Top or bottom boot block configurations
available
s Embedded Algorithms
— Embedded Erase algorithm automatically
pre-programs and erases sectors or entire chip
— Embedded Program algorithm automatically
programs and verifies data at specified address
s Minimum 1 million program/erase cycles
guaranteed per sector
s Package options
— 44-pin SO
— 48-pin TSOP
s Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
— Superior inadvertent write protection
s Data# Polling and Toggle Bits
— Provides a software method of detecting
program or erase cycle completion
s Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or
erase cycle completion
s Erase Suspend/Erase Resume
— Suspends or resumes erasing sectors to allow
reading and programming in other sectors
— No need to suspend if sector is in the other bank
s Hardware reset pin (RESET#)
— Hardware method of resetting the device to
reading array data
Publication# 21606 Rev: C Amendment/0
Issue Date: April 1998