440EPX Datasheet, PDF (84/94 Pages) Applied Micro Circuits Corporation – PowerPC 440EPx Embedded Processor

440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
Table 21. I/O Specifications—400 MHz to 667 MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
External Slave Peripheral Interface
DMAAck0:3
n/a
n/a
DMAReq0:3
4
1
EOT0:3/TC0:3
4
1
PerAddr02:31
4
1
PerBLast
4
1
PerCS0:5
n/a
n/a
PerData00:15
4
1
PerData16:31
4
1
PerOE
n/a
n/a
PerReady
4
1
PerR/W
4
1
PerWBE0:1
4
1
External Master Peripheral Interface
BusReq
n/a
n/a
ExtAck
n/a
n/a
ExtReq
4
1
ExtReset
n/a
n/a
HoldAck
n/a
n/a
HoldReq
4
1
HoldPri
4
1
PerClk
PerErr
4
1
NAND Flash Interface
NFALE
n/a
n/a
NFCE0:3
n/a
n/a
NFCLE
n/a
n/a
NFRdyBusy
4
1
NFREn
n/a
n/a
NFWEn
n/a
n/a
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
6
1
n/a
n/a
6
1
6
1
6
1
6
1
6
1
6
1
6
1
n/a
n/a
6
1
6
1
6
1
6
1
n/a
n/a
6
1
6
1
n/a
n/a
n/a
n/a
n/a
n/a
6
1
6
1
6
1
n/a
n/a
6
1
6
1
Output Current (mA)
I/O H
I/O L
(minimum) (minimum)
19.1
8.7
n/a
n/a
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
14.6
6.6
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
19.1
8.7
n/a
n/a
n/a
n/a
19.1
8.7
n/a
n/a
19.1
8.7
19.1
8.7
19.1
8.7
n/a
n/a
19.1
8.7
19.1
8.7
Clock
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
Notes
1
84
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