440EPX Datasheet, PDF (1/94 Pages) Applied Micro Circuits Corporation – PowerPC 440EPx Embedded Processor

Part Number 440EPx
Revision 1.26 – October 15, 2007
440EPx
PowerPC 440EPx Embedded Processor
Preliminary Data Sheet
Features
• PowerPC^® 440 processor operating up to
667 MHz with 32 KB I-cache and D-cache with
parity checking.
• 16KB of on-chip SRAM.
• Selectable processor:bus clock ratios of N:1, N:2.
• Floating Point Unit with single- and double-
precision and single-cycle throughput.
• Dual bridged Processor Local Buses (PLBs) with
64- and 128-bit widths.
• Double Data Rate 2/1 (DDR2/1) Synchronous
DRAM (SDRAM) interface operating up to
166 MHz (333 MHz data transfer rate) with
optional ECC.
• DMA support for external peripherals, internal
UART and memory.
• Programmable Interrupt Controller supports
interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT).
• PCI V2.2 interface (3.3V only). Thirty-two bits at
up to 66 MHz.
• Two Ethernet 10/100/1000Mbps half- or full-
duplex interfaces. Operational modes supported
are with packet reject, Jumbo frames, and
interrupt coalescing.
• Up to four serial ports (16750 compatible UART).
• One USB 2.0 Device or Host interface with
internal PHY and one USB 2.0 direct Device UTMI
interface.
• External peripheral bus (32-bit data) for up to six
devices with external mastering.
• Two IIC interfaces (one with boot parameter read
capability).
• NAND Flash interface.
• SPI interface.
• General Purpose I/O (GPIO) interface.
• JTAG interface for board level testing.
• Boot from PCI memory, NOR Flash on the
external peripheral bus, or NAND Flash on the
NAND Flash interface.
• Optional security feature (PPC440EPx-S).
• Available in RoHS compliant, lead-free package.
Description
Designed specifically to address high-end embedded
applications, the PowerPC 440EPx (PPC440EPx)
provides a high-performance, low-power solution that
interfaces to a wide range of peripherals and
incorporates on-chip power management features.
This chip contains a high-performance RISC
processor, on-chip SRAM, a floating point unit,
DDR2/1 SDRAM controller, PCI bus interface, control
for external ROM and peripherals, DMA with
scatter/gather support, Ethernet ports, serial ports, IIC
interfaces, SPI interface, USB ports, NAND Flash
interface, an optional security feature
(PPC440EPx-S), and general purpose I/O.
Technology: CMOS Cu-11, 0.13 μm.
Package: 35 mm, 680-ball thermally enhanced plastic
ball grid array (TE-EPBGA). RoHS compliant package
available.
Typical power: Less than 3 W at 533 MHz.
Supply voltages required: 3.3 V, 2.5 V, 1.8 V (DDR2) or
2.5 V (DDR1), 1.5 V.
AMCC Proprietary
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