CS19202CBI30 Datasheet, PDF (2/2 Pages) Applied Micro Circuits Corporation – STS-192 SONET/SDH FRAMER AND POS/ATM MAPPER

Ganges: S19202CBI30
Product Brief Revision 3.1 - January 2002
STS-192 POS/ATM SONET/SDH MAPPER
PRODUCT BRIEF
Overview and Applications
SONET Processing
The S19202CBI30 supports either a single STS-192/
STM-64, or four STS-48/STM-16 SONET/SDH on its pri-
mary line interface as well as on its APS port. It provides
full duplex mapping of ATM cells or packets for STS-
192c/AU-4-64c, STS-48c/AU-4-16c, and/or STS-12c/
AU-4-4c SONET/SDH payloads.
A TOH/SOH interface provides direct add/drop capability
for E1, E2, F1, and both Section and Line DCC channels.
On the transmit side the S19202CBI30 generates sec-
tion, line, and path overhead. It performs framing pattern
insertion (A1, A2), scrambling, alarm signal insertion,
and generates section, line and path Bit Interleaved Par-
ity (B1/B2/B3) for far-end performance monitoring.
On the receive side the S19202CBI30 processes sec-
tion, line, and path overhead. It performs framing (A1,
A2), descrambling, alarm detection, pointer interpreta-
tion, bit interleaved parity monitoring (B1/B2/B3), and
error count accumulation for performance monitoring.
The APS interface is a mirror image of the primary line
interface that also operates either as a single STS-192/
or as four STS-48/STM-16 SONET/SDH Line. This
includes TOH add/drop as well section and line monitor-
ing. This APS port can directly interface to a fiber optics
module or to the APS port of a mate S19202CBI30.
ATM Processing
When configured for ATM cell processing, the
S19202CBI30’s ATM processor(s) will perform all neces-
sary cell processing as defined by ATM UNI3.1 and ITU-
T I.432.1 and I.432.2.
HDLC Processing
When configured for POS mode, the S19202CBI30’s
HDLC processor(s) provide the insertion of HDLC
framed packets into the STS SPE(s)/STM VC(s). The
S19202CBI30 performs HDLC processing as defined by
IETF RFCs 1661, 1662 and 2615. This includes optional
Address/Control field insertion and removal, Frame
Check Sequence (FCS) generation and check, transpar-
ency processing, HDLC frame delineation and optional
X43+1 scrambling and de-scrambling.
The HDLC processor(s) are also compatible with Frame
Relay Forum’s FRF.14 specification.
Line-side Interface
On the main line-side and the APS port, the
S19202CBI30 supports a 16-bit parallel LVDS interface,
operating at 622MHz that is compliant with the OIF SFI-4
recommendation and designed to interface to AMCC’s
S3091/92 and S3097/98 OC-192 physical layer devices.
For quad STS-48/STM-16 operation, the S19202CBI30
supports four 4-bit, 622 MHz, line interfaces and is
designed to interface to AMCC’s S3455 OC-48 physical
layer device.
System Interface
The S19202CBI30 IC provides a 64-bit, 200MHz, Flex-
Bus 4^TM system interface for the transport of either pack-
ets or ATM cells. The S19202CBI30 also includes a clear
channel mode that enables the direct mapping of system
payload from the system interface into Synchronous
Payload Envelope.
The FlexBus 4 interface complies with the OIF SPI-4
specification.
TYPICAL APPLICATION: Ganges in a STS-192/AU-4-64 application with APS
Reference
Clock
Microprocessor
Control
12 16
Control Addr Data
SONET
Line Side
Interface
OC-192
Line Interface
Fiber Optic
Transceiver
SerTxD±
SerRxD±
P/S
SONET XMIT
&
S/P
TX_SONETCLK
TX_DATA[15:0]
RX_LOS_[1]
SONET RCVR _{RX_SONETCLK_[1]}
with
Clk Recovery
RX_DATA[15:0]
AMCC S3091/92
AMCC S3097/98
Protection
Ganges
or
Fiber Optics
Module
APS
System Control SIgnals
GANGES
S19202CBI30
STX_DATA_IN[63:0]
SRX_DATA_OUT[63:0]
NETWORK
PROCESSOR
AMCC
TOH Insertion
and Extraction
200 Minuteman Road, Andover, MA 01810 Ph: [phone] Fax: [phone]