S5935 Datasheet, PDF (159/190 Pages) Applied Micro Circuits Corporation – PCI 5V Bus Master/Target Device 32-bit

PASS-THRU OVERVIEW
CONFIGURATION
The S5935 Pass-Thru interface utilizes four Base Ad-
dress Registers (BADR1:4). Each Base Address
Register corresponds to a Pass-Thru region. The
contents of these registers during initialization deter-
mine the characteristics of that particular Pass-Thru
region. Each region can be mapped to memory or I/O
space. Memory mapped devices can, optionally, be
mapped below 1 Mbyte and can be identified as
prefetchable. Both memory and I/O regions can be
configured as 8-, 16-, or 32-bits wide.
The designer has the option to use 1, 2, 3, 4 or none
of the Pass-Thru regions. Base Address Registers
are loaded during initialization from the external non-
volatile boot device. Without an external boot device,
the default value for the BADR registers is zero (re-
gion disabled). The Base Address Registers are the
only registers that define Pass-Thru operation.
S5935 Base Address Register Definition
Some bits in the Base Address Registers have specific
functions. The following bits have special functions:
D0
Memory or I/O mapping. If this bit is clear,
the region should be memory mapped. If this
bit is set, the region should be I/O mapped.
D2:1
Location of a memory region. These bits
request that the region be mapped in a
particular part of memory. These bit
definitions are only used for memory
mapped regions.
D2 D1 Location
0
0 Anywhere in 32-bit memory space
0
1 Below 1 Mbyte in memory space
(Real Mode address space)
1
0 Anywhere in 64-bit memory space
(not valid for the S5935)
1
1 Reserved
D3
D31:30
Prefetchable. For memory mapped regions,
the region can be defined as cacheable. If
set, the region is cacheable. If this bit is
clear, the region is not.
Pass-Thru region bus width. These two bits
are used by the S5935 to define the data
bus width for a Pass-Thru region. Regard-
less of the programming of other bits in the
BADR register, if D31:30 are zeros, the
Pass-Thru region is disabled.
D31 D30 Add-On Bus Width
0
0 Region disabled
0
1 8-bits
1
0 16-bits
1
1 32-bits
S5935
BADR1:4 bits D31:30 are used only by the S5935.
When the host reads the Base Address Registers
during configuration cycles, they always return the
same value as D29. If D29 is zero, D31:30 return
zero, indicating the region is disabled. If D29 is one,
D31:30 return one. This operation limits each Pass-
Thru region to a maximum size of 512 Mbytes of
memory.
For I/O mapped regions, the PCI specification allows
no more than 256 bytes per region. The S5935 al-
lows larger regions to be requested by the Add-On,
but a PCI BIOS will not allocate the I/O space and
will probably disable the region.
Creating a Pass-Thru Region
Page 3-40 describes the values that must be pro-
grammed into the non-volatile boot device to request
various block sizes and characteristics for Pass-Thru
regions. After reset, the S5935 downloads the con-
tents of the boot device locations 54h, 58h, 5Ch, and
60h into “masks” for the corresponding Base Address
Registers. The following are some examples for vari-
ous Pass-Thru region definitions:
NV Memory Contents Pass-Thru Region Definition
54h = BFFFF002h
Pass-Thru region 1 is a 4Kbyte
region, mapped below 1 Mbyte
in memory space with a 16-bit
Add-On data bus. This memory
region is not cacheable.
58h = 3xxxxxxxh
Pass-Thru region 2 is
disabled. (D31:30 = 00.)
60h = FFFFFF81h
Pass-Thru region 3 is a 32-
bit, 128 byte I/O-mapped
region.
64h = 00000000h
Pass-Thru region 4 is dis-
abled.
During the PCI bus configuration, the host CPU writes
all ones to each Base Address Register, and then
reads the contents of the registers back. The mask
downloaded from the boot device determines which
bits are read back as zeros and which are read back
as ones. The number of zeros read back indicates the
amount of memory or I/O space a particular S5935
Pass-Thru region is requesting.
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