EP5352QI Datasheet, PDF (9/18 Pages) Altera Corporation – 500/600/800mA PowerSoC Synchronous Buck Regulators With Integrated Inductor

Output Voltage Select
To provide the highest degree of flexibility in
choosing output voltage, the EP53x2QI family
uses a 3 pin VID, or Voltage ID, output voltage
select arrangement. This allows the designer
to choose one of seven preset voltages, or to
use an external voltage divider. Internally, the
output of the VID multiplexer sets the value for
the voltage reference DAC, which in turn is
connected to the non-inverting input of the
error amplifier. This allows the use of a single
feedback divider with constant loop gain and
optimum compensation, independent of the
output voltage selected.
Table 1 shows the various VS0-VS2 pin logic
states and the associated output voltage
levels. A logic “1” indicates a connection to V_IN
or to a “high” logic voltage level. A logic “0”
indicates a connection to ground or to a “low”
logic voltage level. These pins can be either
hardwired to V_IN or GND or alternatively can be
driven by standard logic levels. These pins
must not be left floating.
VS2
VS1
VS0
V_OUT
0
0
0
3.3
0
0
1
2.5
0
1
0
2.8
0
1
1
1.2
1
0
0
3.0
1
0
1
1.8
1
1
0
2.7
1
1
1
External
External Voltage Divider
As described above, the external voltage
divider option is chosen by connecting the
VS0, VS1, and VS2 pins to V_IN or logic “high”.
The EP53x2QI uses a separate feedback pin,
V_FB, when using the external divider. VSENSE
must be connected to V_OUT as indicated in
Figure 5.
EP5382QI/EP5362QI/EP5352Q I
Table 1. Voltage select settings.
V_IN
2.2uF
4.7uF
ENABLE
V_in
V_Sense
V_out
VS0
V_FB
VS1
VS2
GND
V_OUT
Ra
10µF
Rb
Figure 5. External Divider.
The output voltage is selected by the following
formula:
( ) V_OUT
= 0.603V
1+
Ra
Rb
R_a must be chosen as 200KΩ to maintain loop
gain. Then R_b is given as:
R ^{= 1.2x105 Ω}
b _{VOUT − 0.603}
Dynamically Adjustable Output
The EP53x2QI are designed to allow for
dynamic switching between the predefined VID
voltage levels The inter-voltage slew rate is
optimized to prevent excess undershoot or
overshoot as the output voltage levels
transition. The slew rate is identical to the soft-
start slew rate of 3V/mS.
Dynamic transitioning between internal VID
settings and the external divider is not allowed.
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before VIN. During power down, the
VIN should not be powered down before the
ENABLE. Tying PVIN and ENABLE together
03132
9
October 11, 2013
www.altera.com/enpirion
Rev H