EP5352QI Datasheet, PDF (8/18 Pages) Altera Corporation – 500/600/800mA PowerSoC Synchronous Buck Regulators With Integrated Inductor

and compact construction of the integrated
inductor reduces the radiated noise that
couples into the traces of the circuit board.
Further, the package layout is optimized to
reduce the electrical path length for the AC
ripple currents that are a major source of
radiated emissions from DCDC converters.
The integrated inductor significantly reduces
parasitic effects that can harm loop stability,
and makes layout very simple.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the V_OUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The EP53x2QI have two soft start operating
modes. When VOUT is programmed using a
preset voltage in VID mode, the device has a
constant slew rate. When the EP53x2QI is
configured in external resistor divider mode,
the device has a constant VOUT ramp time.
Output voltage slew rate and ramp time is
given in the Electrical Characteristics Table.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup.
When operating in VID mode, the maximum
total capacitance on the output, including the
output filter capacitor and bulk and decoupling
capacitance, at the load, is given as:
C_{OUT_TOTAL_MAX} = C_{OUT_Filter} + C_{OUT_BULK} = 350uF
When the EP53x2QI output voltage is
programmed using and external resistor divider
the maximum total capacitance on the output is
given as:
C_{OUT_TOTAL_MAX} = 6.253x10^-4/V_OUT Farads
Application Information
EP5382QI/EP5362QI/EP5352Q I
The above number and formula assume a no
load condition at startup.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling V_OUT low. This condition is maintained
for a period of 1mS and then a normal soft start
is initiated. If the over current condition still
persists, this cycle will repeat in a “hiccup”
mode.
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation. A logic low will disable the converter
and cause it to shut down. A logic high will
enable the converter into normal operation. In
shutdown mode, the device quiescent current
will be less than 1 uA. The ENABLE pin must
not be left floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
03132
8
October 11, 2013
www.altera.com/enpirion
Rev H