5AGXFB3H4F40C5N Datasheet, PDF (60/82 Pages) Altera Corporation – Arria V Device Handbook

2–32
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Table 2–29. High-Speed I/O Specifications for Arria V Devices—Preliminary ^{(1), (2), (3)} (Part 2 of 3)
Symbol
Conditions
–4 Speed Grade
Min Typ Max
–5 Speed Grade
Min Typ Max
Transmitter
True
Differential
I/O Standards
- f_HSDR (data
rate)
SERDES factor J = 3 to 10
SERDES factor J = 1 to 2, Uses
DDR Registers
(7)
—
(7)
—
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
Networks -
f_HSDR (data
rate) ⁽⁸⁾
SERDES factor J = 4 to 10
(7)
—
t_{x Jitter} - True
Differential
I/O Standards
Total Jitter for Data Rate,
600 Mbps - 1.25 Gbps
Total Jitter for Data Rate,
< 600 Mbps
——
——
t_{x Jitter} -
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
Network
Total Jitter for Data Rate,
600 Mbps – 1.25 Gbps
Total Jitter for Data Rate
< 600 Mbps
——
——
TX output clock duty cycle for both
t_DUTY
True and Emulated Differential I/O 45 50
Standards
True Differential I/O Standards — —
t_{RISE &} t_FALL
Emulated Differential I/O
Standards with Three External
Output Resistor Networks
——
TCCS
True Differential I/O Standards
Emulated Differential I/O
Standards
——
——
1250
(7)
TBD
160
0.1
TBD
TBD
55
200
250
150
300
(7)
—
(7)
—
(7)
—
——
——
——
——
45 50
——
——
——
——
1250
(7)
TBD
160
0.1
TBD
TBD
55
200
250
150
300
–6 Speed Grade
Unit
Min Typ Max
(7) _{— 1050 Mbps}
(7)
—
(7) _Mbps
(7)
—
TBD Mbps
— — 160 ps
— — 0.1
UI
— — TBD ps
— — TBD UI
45 50
55
%
— — 200 ps
— — 300 ps
— — 150 ps
— — 300 ps
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation