5AGXFB3H4F40C5N Datasheet, PDF (56/82 Pages) Altera Corporation – Arria V Device Handbook

2–28
Chapter 2: Device Datasheet for Arria V Devices
Switching Characteristics
Table 2–25. PLL Specifications for Arria V Devices—Preliminary ⁽¹⁾ (Part 2 of 3)
Symbol
Parameter
Min
t_LOCK
Time required to lock from end-of-device configuration or
deassertion of areset
—
t_DLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
PLL closed-loop low bandwidth
—
f_CLBW
PLL closed-loop medium bandwidth
—
PLL closed-loop high bandwidth ⁽⁸⁾
—
t_{PLL_PSERR}
Accuracy of PLL phase shift
—
t_ARESET
Minimum pulse width on the areset signal
10
t_INCCJ ^{(4), (5)}
Input clock cycle-to-cycle jitter (F_REF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (F_REF < 100 MHz)
—
—
t_{OUTPJ_DC} ⁽⁶⁾
Period jitter for dedicated clock output (F_OUT ≥ 100 MHz)
Period jitter for dedicated clock output (F_OUT < 100 MHz)
—
—
t_{OUTCCJ_DC} ⁽⁶⁾
Cycle-to-cycle jitter for dedicated clock output
(F_OUT ≥ 100 MHz)
Cycle-to-cycle jitter for dedicated clock output
(F_OUT < 100 MHz)
—
—
t_{OUTPJ_IO} ^(6),
Period Jitter for clock output on the regular I/O
(F_OUT ≥ 100 MHz)
—
(9)
Period Jitter for clock output on the regular I/O
(F_OUT < 100 MHz)
—
Cycle-to-cycle jitter for clock output on the regular I/O
t_{OUTCCJ_IO} ^{(6), (F}OUT ^{≥ 100 MHz)}
—
(9)
Cycle-to-cycle jitter for clock output on the regular I/O
(F_OUT < 100 MHz)
—
t_{OUTPJ_DC_F}
Period jitter for dedicated clock output in fractional mode
—
t_{OUTCCJ_DC_F}
Cycle-to-cycle jitter for dedicated clock output in fractional
mode
—
t_{OUTPJ_IO_F}
Period Jitter for clock output on the regular I/O in fractional
mode
—
t_{OUTCCJ_IO_F}
Cycle-to-cycle jitter for clock output on the regular I/O in
fractional mode
—
Period jitter for dedicated clock output in cascaded PLLs
t_{CASC_OUTPJ_DC} ^(FOUT ^{≥100 MHz)}
—
(6), (7)
Period jitter for dedicated clock output in cascaded PLLs
(F_OUT < 100 MHz)
—
t_DRIFT
Frequency drift after PFDENA is disabled for a duration of
100 µs
—
Typ
Max
Unit
—
1
ms
—
1
ms
0.3
—
MHz
1.5
—
MHz
4
—
MHz
—
±50
ps
—
—
ns
—
0.15
UI (p-p)
—
+750 ps (p-p)
—
TBD ⁽¹⁾ ps (p-p)
—
TBD ⁽¹⁾ mUI (p-p)
—
TBD ⁽¹⁾ ps (p-p)
—
TBD ⁽¹⁾ mUI (p-p)
—
TBD ⁽¹⁾ ps (p-p)
—
TBD ⁽¹⁾ mUI (p-p)
—
TBD ⁽¹⁾ ps (p-p)
—
TBD ⁽¹⁾ mUI (p-p)
—
TBD ⁽¹⁾
—
—
TBD ⁽¹⁾
—
—
TBD ⁽¹⁾
—
—
TBD ⁽¹⁾
—
—
TBD ⁽¹⁾ ps (p-p)
—
TBD ⁽¹⁾ mUI (p-p)
—
±10
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Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation