EP1C6F256C8N Datasheet, PDF (53/385 Pages) Altera Corporation – Cyclone Device Handbook, Volume 1

Global Clock Network and Phase-Locked Loops
Table 2–6 shows the PLL features in Cyclone devices. Figure 2–25 shows
a Cyclone PLL.
Table 2–6. Cyclone PLL Features
Feature
Clock multiplication and division
Phase shift
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
PLL Support
m/(n × post-scale counter) (1)
Down to 125-ps increments (2), (3)
Yes
2
One differential or one single-ended (4)
Notes to Table 2–6:
(1) The m counter ranges from 2 to 32. The n counter and the post-scale counters
range from 1 to 32.
(2) The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
(3) For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
(4) The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
Figure 2–25. Cyclone PLL Note (1)
VCO Phase Selection
Selectable at Each PLL
Output Port
Post-Scale
Counters
CLK0 or
LVDSCLK1p (2)
CLK1 or
LVDSCLK1n (2)
÷n
Δt
PFD (3)
Charge
Pump
Loop
Filter
VCO
Δt
÷m
÷g0
Global clock
÷g1
Global clock
÷e
I/O buffer
Notes to Figure 2–25:
(1) The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
(2) LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0 pin’s secondary
function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2 pin’s secondary
function is LVDSCLK2p and the CLK3 pin’s secondary function is LVDSCLK2n.
(3) PFD: phase frequency detector.
Altera Corporation
May 2008
2–33
Preliminary