EP1C6F256C8N Datasheet, PDF (173/385 Pages) Altera Corporation – Cyclone Device Handbook, Volume 1

Using M4K Memory
M4K memory blocks can operate in various modes, including:
■ Single-port
■ Simple dual-port
■ True dual-port (bidirectional dual-port)
■ Shift-register
■ ROM
■ FIFO
Implementing Single-Port Mode
Single-port mode supports non-simultaneous read and write operations.
Figure 7–2 shows the single-port memory configuration for M4K blocks.
Figure 7–2. Single-Port Memory Note (1)
data[ ]
address[ ]
wren
inclock
inclocken
inaclr
q[ ]
outclock
outclocken
outaclr
Note to Figure 7–2:
(1) Two single-port memory blocks can be implemented in a single M4K block.
M4K memory blocks can also be divided in half and used for two
independent single-port RAM blocks. The Quartus II software
automatically uses this method of single-port memory packing when
running low on memory resources. When deliberately assigning two
single-port memories to one M4K block, first ensure that each of the two
independent RAM blocks is equal to or less than half the size of the M4K
block.
In the single-port RAM configuration, the outputs can only be in read-
during-write mode, which means that during the write operation, data
written to the RAM flows through to the RAM outputs. When the output
registers are bypassed, the new data is available on the rising edge of the
same clock cycle on which it was written.
For more information about read-during-write mode, see “Read-during-
Write Operation at the Same Address” on page 7–20.
Figure 7–3 shows timing waveforms for read and write operations in
single-port mode.
Altera Corporation
May 2008
7–5
Preliminary