M-CAS-C8237 Datasheet, PDF (5/5 Pages) Altera Corporation – PROGRAMMABLE DMA CONTROLLER ALTERA CORE

Temporary Word Count Register (16 Bit Decrementor)
It will decrement the word count after each transfer. When the
value in the register goes from zero to FFFFH, a Terminal
Count (TC) will be generated.
Temporary Address Register (16 Bit Incremen-
tor/Decrementor)
Base on the mode of the address, the address will be decre-
mented or incremented after each transfer. And the
intermediate values of the address are stored in the Current
Address register during the transfer.
Implementation Results
The following are typical performance and utilization results us-
ing a variety of Altera devices.
Supported Device
Family
Tested
Cyclone
Stratix
Stratix-II
EP1C20-6
EP1S20-5
EP2S60-3
LEs
1,007
1,007
816
Utilization
Memory Memory
bits
0
0
0
0
0
0
Performance
F_max
97 MHz
94 MHz
140 MHz
Support
The core as delivered is warranted against defects for three
years from purchase. Thirty days of phone and email technical
support are included, starting with the first interaction. Addi-
tional maintenance and support options are available.
Verification
The core has been verified through extensive simulation and
rigorous code coverage measurements.
Deliverables
The core includes everything required for successful implemen-
tation:
Encrypted Licenses
• Post-synthesis EDIF netlist
• Assignment & Configuration
• Symbol file
• Include file
• Wrapper for matching the I/O of the original device
• Vectors for testbench
HDL Source Licenses
• VHDL or Verilog RTL source code
• Testbench
• Wrapper for matching the I/O of the original device
• Vectors for testbench
• Expected results for testbench
• Simulation and synthesis script
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Contents subject to change without notice. July 2003