M-CAS-C8237 Datasheet, PDF (4/5 Pages) Altera Corporation – PROGRAMMABLE DMA CONTROLLER ALTERA CORE

Temporary Register
Read Temporary Register Command:
A3 A2 A1 A0 IORN IOWN
11010
1
This register is used to hold data during memory-to-memory
transfers. Following the completion of the transfers, the last
word moved can be read by the microprocessor. The tempo-
rary register is cleared by a Reset.
Current Address Register
Each channel has a 16-bit Current Address register. This reg-
ister holds the value of the address used during DMA
transfers. The address is automatically incremented or dec-
remented after each transfer and the intermediate values of
the address are stored in the Current Address register during
the transfer. This register is written or read by the microproc-
essor.
Current Word Register
Each channel has a 16-bit Current Word Count register. This
register determines the number of transfers to be performed.
The word count is decremented after each transfer. When the
value in the register goes from zero to FFFFH, a TC will be
generated. This register is loaded or read by the microproc-
essor in the Program Condition.
Base Address and Base Word Count Registers
Each channel has a 16-bit Base Address and 16-bit Base
Word Count register. These registers store the original value,
which will be loaded to current registers during Auto initialize.
Word Count and Address Register Command Codes
Write -> CSN = 0, IORN = 1 and IOWN = 0
Read -> CSN = 0, IORN = 0 and IOWN = 1
Register
A3 A2 A1 A0 FF DB0-DB7
CH 0
0 A0-A7
Base and
0 0 0 0 _{1 A8-A15}
Current Address
CH 0
0 W0-W7
Base and Cur-
0 0 0 1 _{1 W8-W15}
rent Word Count
CH 1
0 A0-A7
Base and
0 0 1 0 _{1 A8-A15}
Current Address
CH 1
0 W0-W7
Base and Cur-
0 0 1 1 _{1 W8-W15}
rent Word Count
CH 2
0 A0-A7
Base and
0 1 0 0 _{1 A8-A15}
Current Address
CH 2
0 W0-W7
Base and Cur-
0 1 0 1 _{1 W8-W15}
rent Word Count
CH 3
0 A0-A7
Base and
0 1 1 0 _{1 A8-A15}
Current Address
CH 3
0 W0-W7
Base and Cur-
0 1 1 1 _{1 W8-W15}
rent Word Count
Software Commands
These three commands do not depend on any specific bit
pattern on the data bus.
Clear First/Last Flip-Flop Command:
A3 A2 A1 A0 IORN IOWN
11001
0
This command must be executed prior to writing or reading
new address or word count information to the C8237.
Master Clear Command:
A3 A2 A1 A0 IORN IOWN
11011
0
This command has the same effect as the hardware Reset.
The Command, Status, Request, Temporary, and Internal
First/Last Flip-Flop registers are cleared and the Mask regis-
ter is set. The C8237 will be in the idle cycle.
Clear Mask Register Command:
A3 A2 A1 A0 IORN IOWN
11101
0
This command clears the mask bits of all four channels, ena-
bling them to accept DMA requests
Cast, Inc.
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