EP53A7LQI Datasheet, PDF (3/19 Pages) Altera Corporation – 1A PowerSoC Light Load Mode Buck Regulator with Integrated Inductor

PIN
9, 10,
11
12
13
14
NAME
VS2, VS1,
VS0
ENABLE
AVIN
PVIN
EP53A7LQI/EP53A7HQI
FUNCTION
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP53A7LQI: Selects one of seven preset output voltages or an external resistor divider.
EP53A7HQI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.)
Output Enable. Enable = logic high; Disable = logic low
Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor.
Input Voltage for the MOSFET switches.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: ENABLE, V_SENSE, V_SO – V_S2
Voltages on: V_FB (EP53A7LQI)
Maximum Operating Junction Temperature
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
SYMBOL
V_IN
T_J-ABS
T_STG
MIN
-0.3
-0.3
-0.3
-65
MAX
6.0
V_IN+ 0.3
2.7
150
150
260
2000
UNITS
V
V
V
°C
°C
°C
V
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
V_IN
T_A
T_J
MIN
2.4
- 40
- 40
MAX
5.5
+85
+125
UNITS
V
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient –0 LFM (Note 1)
Thermal Overload Trip Point
Thermal Overload Trip Point Hysteresis
SYMBOL
θ_JA
T_J-TP
TYP
80
+155
25
UNITS
°C/W
°C
°C
Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards
01543
3
October 11, 2013
www.altera.com/enpirion
Rev D