EPM7160STC100-10 Datasheet, PDF (29/66 Pages) Altera Corporation – Programmable Logic Device Family

MAX 7000 Programmable Logic Device Family Data Sheet
Figure 12. MAX 7000 Timing Model
Input
Delay
t_IN
PIA
Delay
t _PIA
Internal Output
Enable Delay
t _{IOE (1)}
Global Control
Delay
t _GLOB
Logic Array
Delay
t _LAD
Register
Control Delay
t _LAC
t_IC
t _EN
Shared
Expander Delay
t _SEXP
Parallel
Expander Delay
t _PEXP
Register
Delay
t _SU
t_H
t _PRE
t _CLR
t _RD
t _COMB
t _FSU
t _FH
Fast
Input Delay
t _{F I N} (1)
Output
Delay
t _OD1
t _{OD2 (2)}
t _OD3
t _XZ
t _{Z X1}
t _ZX2 (2)
t _{ZX3 (1)}
I/O
Delay
t_IO
Notes:
(1) Only available in MAX 7000E and MAX 7000S devices.
(2) Not available in 44-pin devices.
f
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 13 shows the internal timing
relationship of internal and external delay parameters.
For more infomration, see Application Note 94 (Understanding MAX 7000
Timing).
Altera Corporation
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